packet_router: moved dsp framer into a module, added clr to splitter and renamed

4 files changed, 110 insertions, 93 deletions

diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index 0508c6b77..5552fbd51 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -9,6 +9,7 @@ FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \
 buffer_int.v \
 buffer_pool.v \
 crossbar36.v \
+dsp_framer36.v \
 fifo_2clock.v \
 fifo_2clock_cascade.v \
 ll8_shortfifo.v \
@@ -23,7 +24,7 @@ fifo36_to_fifo19.v \
 fifo19_to_fifo36.v \
 fifo36_mux.v \
 fifo36_demux.v \
-fifo36_splitter.v \
 packet_router.v \
+splitter36.v \
 valve36.v \
 ))
diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v
new file mode 100644
index 000000000..fbdc9fbd7
--- /dev/null
+++ b/usrp2/fifo/dsp_framer36.v
@@ -0,0 +1,98 @@
+
+// Frame DSP packets with a header line to be handled by the protocol machine
+
+module dsp_framer36
+    #(parameter BUF_SIZE = 9)
+    (
+        input clk, input rst, input clr,
+        input [35:0] inp_data, input inp_valid, output inp_ready,
+        output [35:0] out_data, output out_valid, input out_ready
+    );
+
+    localparam DSP_FRM_STATE_WAIT_SOF = 0;
+    localparam DSP_FRM_STATE_WAIT_EOF = 1;
+    localparam DSP_FRM_STATE_WRITE_HDR = 2;
+    localparam DSP_FRM_STATE_WRITE = 3;
+
+    reg [1:0] dsp_frm_state;
+    reg [BUF_SIZE-1:0] dsp_frm_addr;
+    reg [BUF_SIZE-1:0] dsp_frm_count;
+    wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1;
+
+    //DSP input stream ready in the following states
+    assign inp_ready =
+        (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : (
+        (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : (
+    1'b0));
+
+    //DSP framer output data mux (header or BRAM):
+    //The header is generated here from the count.
+    wire [31:0] dsp_frm_data_bram;
+    wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00};
+    assign out_data =
+        (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : (
+        (dsp_frm_addr == dsp_frm_count)           ? {4'b0010, dsp_frm_data_bram}    : (
+    {4'b0000, dsp_frm_data_bram}));
+    assign out_valid = (
+        (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) ||
+        (dsp_frm_state == DSP_FRM_STATE_WRITE)
+    )? 1'b1 : 1'b0;
+
+    RAMB16_S36_S36 dsp_frm_buff(
+        //port A = DSP input interface (writes to BRAM)
+        .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0),
+        .ENA(inp_ready),.SSRA(0),.WEA(inp_ready),
+        //port B = DSP framer interface (reads from BRAM)
+        .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0),
+        .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0)
+    );
+
+    always @(posedge clk)
+    if(rst | clr) begin
+        dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
+        dsp_frm_addr <= 0;
+    end
+    else begin
+        case(dsp_frm_state)
+        DSP_FRM_STATE_WAIT_SOF: begin
+            if (inp_ready & inp_valid & inp_data[32]) begin
+                dsp_frm_addr <= dsp_frm_addr_next;
+                dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF;
+            end
+        end
+
+        DSP_FRM_STATE_WAIT_EOF: begin
+            if (inp_ready & inp_valid) begin
+                if (inp_data[33]) begin
+                    dsp_frm_count <= dsp_frm_addr_next;
+                    dsp_frm_addr <= 0;
+                    dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR;
+                end
+                else begin
+                    dsp_frm_addr <= dsp_frm_addr_next;
+                end
+            end
+        end
+
+        DSP_FRM_STATE_WRITE_HDR: begin
+            if (out_ready & out_valid) begin
+                dsp_frm_addr <= dsp_frm_addr_next;
+                dsp_frm_state <= DSP_FRM_STATE_WRITE;
+            end
+        end
+
+        DSP_FRM_STATE_WRITE: begin
+            if (out_ready & out_valid) begin
+                if (out_data[33]) begin
+                    dsp_frm_addr <= 0;
+                    dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
+                end
+                else begin
+                    dsp_frm_addr <= dsp_frm_addr_next;
+                end
+            end
+        end
+        endcase //dsp_frm_state
+    end
+
+endmodule //dsp_framer36
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
index 1023df2e5..8bd687c5a 100644
--- a/usrp2/fifo/packet_router.v
+++ b/usrp2/fifo/packet_router.v
@@ -528,8 +528,8 @@ module packet_router
     wire        _sp_split_to_mux_valid;
     wire        _sp_split_to_mux_ready;
 
-    fifo36_splitter crs_out_src0(
-        .clk(stream_clk), .rst(stream_rst | stream_clr),
+    splitter36 crs_out_src0(
+        .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
         .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready),
         .out0_data(_sp_split_to_mux_data),    .out0_valid(_sp_split_to_mux_valid),    .out0_ready(_sp_split_to_mux_ready),
         .out1_data(cpu_out_data),             .out1_valid(cpu_out_valid),             .out1_ready(cpu_out_ready)
@@ -544,96 +544,14 @@ module packet_router
 
     ////////////////////////////////////////////////////////////////////
     // DSP input framer
-    //   - add a 1-line frame header to each DSP input packet
-    //   - each header is composed of a byte count and flags
     ////////////////////////////////////////////////////////////////////
 
-    localparam DSP_FRM_STATE_WAIT_SOF = 0;
-    localparam DSP_FRM_STATE_WAIT_EOF = 1;
-    localparam DSP_FRM_STATE_WRITE_HDR = 2;
-    localparam DSP_FRM_STATE_WRITE = 3;
-
-    reg [1:0] dsp_frm_state;
-    reg [BUF_SIZE-1:0] dsp_frm_addr;
-    reg [BUF_SIZE-1:0] dsp_frm_count;
-    wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1;
-
-    //DSP input stream ready in the following states
-    assign dsp_inp_ready =
-        (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : (
-        (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : (
-    1'b0));
-
-    //DSP framer output data mux (header or BRAM):
-    //The header is generated here from the count.
-    wire [31:0] dsp_frm_data_bram;
-    wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00};
-    assign dsp_frm_data =
-        (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : (
-        (dsp_frm_addr == dsp_frm_count)           ? {4'b0010, dsp_frm_data_bram}    : (
-    {4'b0000, dsp_frm_data_bram}));
-    assign dsp_frm_valid = (
-        (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) ||
-        (dsp_frm_state == DSP_FRM_STATE_WRITE)
-    )? 1'b1 : 1'b0;
-
-    RAMB16_S36_S36 dsp_frm_buff(
-        //port A = DSP input interface (writes to BRAM)
-        .DOA(),.ADDRA(dsp_frm_addr),.CLKA(stream_clk),.DIA(dsp_inp_data[31:0]),.DIPA(4'h0),
-        .ENA(dsp_inp_ready),.SSRA(0),.WEA(dsp_inp_ready),
-        //port B = DSP framer interface (reads from BRAM)
-        .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0),
-        .ENB(dsp_frm_ready & dsp_frm_valid),.SSRB(0),.WEB(1'b0)
+    dsp_framer36 #(.BUF_SIZE(BUF_SIZE)) dsp0_framer36(
+        .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
+        .inp_data(dsp_inp_data), .inp_valid(dsp_inp_valid), .inp_ready(dsp_inp_ready),
+        .out_data(dsp_frm_data), .out_valid(dsp_frm_valid), .out_ready(dsp_frm_ready)
     );
 
-    always @(posedge stream_clk)
-    if(stream_rst | stream_clr) begin
-        dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
-        dsp_frm_addr <= 0;
-    end
-    else begin
-        case(dsp_frm_state)
-        DSP_FRM_STATE_WAIT_SOF: begin
-            if (dsp_inp_ready & dsp_inp_valid & dsp_inp_data[32]) begin
-                dsp_frm_addr <= dsp_frm_addr_next;
-                dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF;
-            end
-        end
-
-        DSP_FRM_STATE_WAIT_EOF: begin
-            if (dsp_inp_ready & dsp_inp_valid) begin
-                if (dsp_inp_data[33]) begin
-                    dsp_frm_count <= dsp_frm_addr_next;
-                    dsp_frm_addr <= 0;
-                    dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR;
-                end
-                else begin
-                    dsp_frm_addr <= dsp_frm_addr_next;
-                end
-            end
-        end
-
-        DSP_FRM_STATE_WRITE_HDR: begin
-            if (dsp_frm_ready & dsp_frm_valid) begin
-                dsp_frm_addr <= dsp_frm_addr_next;
-                dsp_frm_state <= DSP_FRM_STATE_WRITE;
-            end
-        end
-
-        DSP_FRM_STATE_WRITE: begin
-            if (dsp_frm_ready & dsp_frm_valid) begin
-                if (dsp_frm_data[33]) begin
-                    dsp_frm_addr <= 0;
-                    dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
-                end
-                else begin
-                    dsp_frm_addr <= dsp_frm_addr_next;
-                end
-            end
-        end
-        endcase //dsp_frm_state
-    end
-
     ////////////////////////////////////////////////////////////////////
     // Assign debugs
     ////////////////////////////////////////////////////////////////////
diff --git a/usrp2/fifo/fifo36_splitter.v b/usrp2/fifo/splitter36.v
index cf1978c34..ed998b4f5 100644
--- a/usrp2/fifo/fifo36_splitter.v
+++ b/usrp2/fifo/splitter36.v
@@ -1,9 +1,9 @@
 
 // Split packets from a fifo based interface so it goes out identically on two interfaces
 
-module fifo36_splitter
+module splitter36
     (
-        input clk, input rst,
+        input clk, input rst, input clr,
         input [35:0] inp_data, input inp_valid, output inp_ready,
         output [35:0] out0_data, output out0_valid, input out0_ready,
         output [35:0] out1_data, output out1_valid, input out1_ready
@@ -32,7 +32,7 @@ module fifo36_splitter
     assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0;
 
     always @(posedge clk)
-    if (rst) begin
+    if (rst | clr) begin
         state <= STATE_COPY_BOTH;
     end
     else begin
@@ -65,4 +65,4 @@ module fifo36_splitter
 
 
 
-endmodule //fifo36_splitter
+endmodule //splitter36