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author | Matt Ettus <matt@ettus.com> | 2010-06-01 16:20:24 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-06-01 16:20:24 -0700 |
commit | 552c3477734c6c302c53fe039d6e85134fcf210c (patch) | |
tree | 7231f8d866c4553d7d19f495b30f04ff28abc356 | |
parent | e5bc7a493252753ad9ddf6799e986fa19841221a (diff) | |
download | uhd-552c3477734c6c302c53fe039d6e85134fcf210c.tar.gz uhd-552c3477734c6c302c53fe039d6e85134fcf210c.tar.bz2 uhd-552c3477734c6c302c53fe039d6e85134fcf210c.zip |
assign addresses for the settings regs
-rw-r--r-- | usrp2/top/u1e/u1e_core.v | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 002b28f7a..ed4176ca5 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -27,11 +27,12 @@ module u1e_core localparam TXFIFOSIZE = 11; localparam RXFIFOSIZE = 11; - localparam SR_TIME64 = 0; - localparam SR_RX_DSP = 0; - localparam SR_RX_CTRL = 0; - localparam SR_TX_DSP = 0; - localparam SR_TX_CTRL = 0; + + localparam SR_RX_DSP = 0; // 7 regs + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_TIME64 = 28; // 4 regs wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; |