async gpmc progress

4 files changed, 173 insertions, 18 deletions

diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v
new file mode 100644
index 000000000..4f253e1b5
--- /dev/null
+++ b/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -0,0 +1,45 @@
+
+// Assumes an asynchronous GPMC cycle
+//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
+//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+//   If there is a bus error, we should be reset
+
+module fifo_to_gpmc_async
+  (input clk, input reset, input clear,
+   input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [15:0] EM_D, input EM_NCS, input EM_NOE,
+   input [15:0] frame_len, output reg bus_error);
+
+   // Synchronize the async control signals
+   reg [1:0] 	cs_del, oe_del;
+   reg [15:0] 	counter;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  cs_del <= 2'b11;
+	  oe_del <= 2'b11;
+       end
+     else
+       begin
+	  cs_del <= { cs_del[0], EM_NCS };
+	  oe_del <= { oe_del[0], EM_NOE };
+       end
+
+   //wire do_read = (~cs_del[0] & (oe_del == 2'b10));
+   wire do_read = (~cs_del[1] & (oe_del == 2'b01));  // change output on trailing edge
+   wire first_read = (counter == 0);
+   wire last_read = ((counter+1) == frame_len);
+
+   assign EM_D = data_i[15:0];
+
+   assign dst_rdy_o = do_read;
+
+   always @(posedge clk)
+     if(reset)
+       bus_error <= 0;
+     else if(dst_rdy_o & ~src_rdy_i)
+       bus_error <= 1;
+   
+
+endmodule // fifo_to_gpmc_async
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
new file mode 100644
index 000000000..c4cf0ef89
--- /dev/null
+++ b/usrp2/gpmc/gpmc_async.v
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpmc_async
+  (// GPMC signals
+   input arst,
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+   
+   // GPIOs for FIFO signalling
+   output rx_have_data, output tx_have_space, output bus_error, input bus_reset,
+   
+   // Wishbone signals
+   input wb_clk, input wb_rst,
+   output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+   output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+
+   // FIFO interface
+   input fifo_clk, input fifo_rst,
+   output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+   input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+
+   output [31:0] debug
+   );
+
+   wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	EM_D_fifo;
+   wire [15:0] 	EM_D_wb;
+
+   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
+
+   wire 	bus_error_tx, bus_error_rx;
+   assign bus_error = bus_error_tx | bus_error_rx;
+   
+   // CS4 is RAM_2PORT for DATA PATH (high-speed data)
+   //    Writes go into one RAM, reads come from the other
+   // CS6 is for CONTROL PATH (wishbone)
+
+   // ////////////////////////////////////////////
+   // TX Data Path
+
+   wire [17:0] 	tx18_data, tx18b_data;
+   wire 	tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [15:0] 	tx_fifo_space, tx_frame_len;
+   
+   assign tx_frame_len = 10;
+   
+   gpmc_to_fifo_async gpmc_to_fifo_async
+     (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
+      .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+      .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
+      .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
+      .bus_error(bus_error_tx) );
+   
+   fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
+      .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
+
+   fifo19_to_fifo36 f19_to_f36
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
+      .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
+   
+   // ////////////////////////////////////////////
+   // RX Data Path
+
+   wire [17:0] 	rx18_data, rx18b_data;
+   wire 	rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+   wire [15:0] 	rx_fifo_space, rx_frame_len;
+   assign rx_frame_len = tx_frame_len;
+   
+   fifo36_to_fifo18 f18_to_f36
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
+      .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) );
+
+   fifo_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
+      .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied());
+
+   fifo_to_gpmc_async fifo_to_gpmc_async
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
+      .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
+      .frame_len(rx_frame_len), .bus_error(bus_error_rx) );
+
+   fifo_watcher fifo_watcher
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]),
+      .have_packet(), .length(), .next() );
+
+   assign rx_have_data = 0;
+   
+   // ////////////////////////////////////////////
+   // Control path on CS6
+   
+   gpmc_wb gpmc_wb
+     (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+      .wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
+      .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
+      .wb_ack_i(wb_ack_i) );
+   
+      assign debug = 0;
+   
+endmodule // gpmc_async
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 31e4fcb69..5fc8134fb 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -21,9 +21,9 @@ module tb_u1e();
    wire [1:0]  EM_NBE;
    
    reg  clk_fpga = 0, rst_fpga = 1;
-   always #15.625 clk_fpga = ~clk_fpga;
+   always #15625 clk_fpga = ~clk_fpga;
 
-   initial #200
+   initial #200000
      @(posedge clk_fpga)
        rst_fpga <= 0;
    
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 7df7b0a48..40950bf82 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -35,22 +35,24 @@ module u1e_core
    wire [35:0] 	 tx_data, rx_data;
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy;
    
-   gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
-	      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
-	      .EM_NOE(EM_NOE),
-
-	      .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
-	      
-	      .wb_clk(wb_clk), .wb_rst(wb_rst),
-	      .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
-	      .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
-	      .wb_ack_i(m0_ack),
-
-	      .fifo_clk(wb_clk), .fifo_rst(wb_rst),
-	      .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
-	      .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
-	      
-	      .debug(debug_gpmc));
+   gpmc_async gpmc (.arst(wb_rst),
+		    .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		    .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
+		    .EM_NOE(EM_NOE),
+		    
+		    .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+		    .bus_error(), .bus_reset(0),
+		    
+		    .wb_clk(wb_clk), .wb_rst(wb_rst),
+		    .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
+		    .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
+		    .wb_ack_i(m0_ack),
+		    
+		    .fifo_clk(wb_clk), .fifo_rst(wb_rst),
+		    .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
+		    .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
+		    
+		    .debug(debug_gpmc));
 
    fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo
      (.clk(wb_clk), .reset(wb_rst), .clear(0),