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| author | Josh Blum <josh@joshknows.com> | 2011-01-07 11:37:52 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-01-07 11:37:52 -0800 |
| commit | 0ea88d916515fffb78cefa6ab46191f7557e2fa3 (patch) | |
| tree | 2cdf06864ead29a1c27a2ce8c5be69ebd5bac401 | |
| parent | 71b24ebf00d5549c97e1341594948232e33b1807 (diff) | |
| download | uhd-0ea88d916515fffb78cefa6ab46191f7557e2fa3.tar.gz uhd-0ea88d916515fffb78cefa6ab46191f7557e2fa3.tar.bz2 uhd-0ea88d916515fffb78cefa6ab46191f7557e2fa3.zip | |
packet_router: tweak mode SR (its only 1 bit)
| -rw-r--r-- | usrp2/fifo/packet_router.v | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index ff1f80927..161b59016 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -68,11 +68,10 @@ module packet_router //setting register for mode control wire [31:0] _sreg_mode_ctrl; - wire master_mode_flag = _sreg_mode_ctrl[0]; - setting_reg #(.my_addr(CTRL_BASE+0)) sreg_mode_ctrl( + setting_reg #(.my_addr(CTRL_BASE+0), .width(1)) sreg_mode_ctrl( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), - .out(_sreg_mode_ctrl),.changed() + .out(master_mode_flag),.changed() ); //setting register to program the IP address |