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| author | Matt Ettus <matt@ettus.com> | 2010-06-08 14:16:22 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-06-08 14:16:22 -0700 |
| commit | 724af67a222aca01207cda9e0e4a8ce33217b7b8 (patch) | |
| tree | 0723810799c76e5b471e65e26f5d1f8fdfa3c2f3 | |
| parent | 6eb6050269f469b982843b526eff80b37e8c5f3b (diff) | |
| download | uhd-724af67a222aca01207cda9e0e4a8ce33217b7b8.tar.gz uhd-724af67a222aca01207cda9e0e4a8ce33217b7b8.tar.bz2 uhd-724af67a222aca01207cda9e0e4a8ce33217b7b8.zip | |
debug pins
| -rw-r--r-- | usrp2/gpmc/fifo_watcher.v | 4 | ||||
| -rw-r--r-- | usrp2/gpmc/gpmc_async.v | 7 | ||||
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 3 |
3 files changed, 10 insertions, 4 deletions
diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index 4bba142b0..fe4e35de3 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -4,13 +4,15 @@ module fifo_watcher (input clk, input reset, input clear, input src_rdy1, input dst_rdy1, input sof1, input eof1, input src_rdy2, input dst_rdy2, input sof2, input eof2, - output reg have_packet, output [15:0] length, output reg bus_error); + output reg have_packet, output [15:0] length, output reg bus_error, + output [31:0] debug); wire write = src_rdy1 & dst_rdy1 & eof1; wire read = src_rdy2 & dst_rdy2 & eof2; wire have_packet_int; reg [15:0] counter; wire [4:0] pkt_count; + assign debug = pkt_count; fifo_short #(.WIDTH(16)) frame_lengths (.clk(clk), .reset(reset), .clear(clear), diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 1050cef7d..9f7b6dc4c 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -105,11 +105,14 @@ module gpmc_async .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), .frame_len(rx_frame_len) ); + wire [31:0] pkt_count; + fifo_watcher fifo_watcher (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), - .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) ); + .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx), + .debug(pkt_count)); // //////////////////////////////////////////// // Control path on CS6 @@ -122,6 +125,6 @@ module gpmc_async .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i) ); - assign debug = 0; + assign debug = pkt_count; endmodule // gpmc_async diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 6dae653ce..dde81df6b 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -430,6 +430,7 @@ module u1e_core assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, - {3'b0, bus_error, misc_gpio[11:0]} }; + {2'b0, bus_error, debug_gpmc[4:0] }, + {misc_gpio[7:0]} }; endmodule // u1e_core |