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| author | Matt Ettus <matt@ettus.com> | 2011-04-18 14:13:50 -0700 | 
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-08 10:52:51 -0700 | 
| commit | 90c74cd45885ab2aba3d090a8deebd11b96c6d7c (patch) | |
| tree | cc2bad819627c06804074bee359f9b8050b6dc94 | |
| parent | 7b127e2f51f636baf1d39f46cc9afd09579bf74f (diff) | |
| download | uhd-90c74cd45885ab2aba3d090a8deebd11b96c6d7c.tar.gz uhd-90c74cd45885ab2aba3d090a8deebd11b96c6d7c.tar.bz2 uhd-90c74cd45885ab2aba3d090a8deebd11b96c6d7c.zip  | |
u2/u2p: use new rx_frontend in u2 and u2p
| -rw-r--r-- | usrp2/sdr_lib/rx_frontend.v | 4 | ||||
| -rw-r--r-- | usrp2/top/N2x0/u2plus_core.v | 15 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 4 | 
3 files changed, 17 insertions, 6 deletions
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index 3b05a4a08..0ad83f6c7 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -69,7 +69,7 @@ module rx_frontend       (.clk(clk), .rst(rst),         .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final)); -   assign i_out = i_final[23:6]; -   assign q_out = q_final[23:6]; +   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i (.clk(clk), .reset(rst), .in(i_final), .out(i_out)); +   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q (.clk(clk), .reset(rst), .in(q_final), .out(q_out));  endmodule // rx_frontend diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index 8a7c6ddee..3d67b0dcf 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -584,6 +584,17 @@ module u2plus_core        .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) );     // ///////////////////////////////////////////////////////////////////////// +   // ADC Frontend +   wire [17:0] 	 adc_i, adc_q; +    +   rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend +     (.clk(dsp_clk),.rst(dsp_rst), +      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), +      .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), +      .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), +      .i_out(adc_i), .q_out(adc_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); +    +   // /////////////////////////////////////////////////////////////////////////     // DSP RX 0     wire [31:0] 	 sample_rx0;     wire 	 clear_rx0, strobe_rx0; @@ -594,7 +605,7 @@ module u2plus_core     dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0       (.clk(dsp_clk),.rst(dsp_rst),        .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), -      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), +      .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),        .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),        .debug() ); @@ -622,7 +633,7 @@ module u2plus_core     dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1       (.clk(dsp_clk),.rst(dsp_rst),        .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), -      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), +      .adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),        .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),        .debug() ); diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 151ac27ae..0821277cc 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -283,7 +283,7 @@ module u2_core        .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),        .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); -   ////////////////////////////////////////////////////////////////////////////////////////// +   // ////////////////////////////////////////////////////////////////////////////////////////     // Reset Controller     system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),  			   .ram_loader_rst_o(ram_loader_rst), @@ -586,7 +586,7 @@ module u2_core     // ADC Frontend     wire [17:0] 	 adc_i, adc_q; -   rx_frontend #(.BASE()) rx_frontend +   rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend       (.clk(dsp_clk),.rst(dsp_rst),        .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),        .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),  | 
