summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJosh Blum <josh@joshknows.com>2011-01-11 12:16:33 -0800
committerJosh Blum <josh@joshknows.com>2011-01-11 12:24:38 -0800
commitd7a8b451d27553b0313917e66255214822ed492b (patch)
tree6ba26deac5d0d061d7dcc3f4e0d9e59a9c553e8a
parentacec75d5f0a20701cfd357ebefe6e59a35f4a948 (diff)
downloaduhd-d7a8b451d27553b0313917e66255214822ed492b.tar.gz
uhd-d7a8b451d27553b0313917e66255214822ed492b.tar.bz2
uhd-d7a8b451d27553b0313917e66255214822ed492b.zip
xbar and valve: fix switching delayed by active signal
-rw-r--r--usrp2/fifo/crossbar36.v12
-rw-r--r--usrp2/fifo/valve36.v9
2 files changed, 12 insertions, 9 deletions
diff --git a/usrp2/fifo/crossbar36.v b/usrp2/fifo/crossbar36.v
index d90f5659c..2a046d8bf 100644
--- a/usrp2/fifo/crossbar36.v
+++ b/usrp2/fifo/crossbar36.v
@@ -9,6 +9,8 @@ module crossbar36
output [35:0] data1_o, output src1_rdy_o, input dst1_rdy_i);
reg cross_int, active0, active1;
+ wire active0_next = (src0_rdy_i & dst0_rdy_o)? ~data0_i[33] : active0;
+ wire active1_next = (src1_rdy_i & dst1_rdy_o)? ~data1_i[33] : active1;
assign data0_o = cross_int ? data1_i : data0_i;
assign data1_o = cross_int ? data0_i : data1_i;
@@ -22,19 +24,19 @@ module crossbar36
always @(posedge clk)
if(reset | clear)
active0 <= 0;
- else if(src0_rdy_i & dst0_rdy_o)
- active0 <= ~data0_i[33];
+ else
+ active0 <= active0_next;
always @(posedge clk)
if(reset | clear)
active1 <= 0;
- else if(src1_rdy_i & dst1_rdy_o)
- active1 <= ~data1_i[33];
+ else
+ active1 <= active1_next;
always @(posedge clk)
if(reset | clear)
cross_int <= 0;
- else if(~active0 & ~active1)
+ else if(~active0_next & ~active1_next)
cross_int <= cross;
endmodule // crossbar36
diff --git a/usrp2/fifo/valve36.v b/usrp2/fifo/valve36.v
index b4b23e5a6..d45eee497 100644
--- a/usrp2/fifo/valve36.v
+++ b/usrp2/fifo/valve36.v
@@ -7,7 +7,8 @@ module valve36
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
reg shutoff_int, active;
-
+ wire active_next = (src_rdy_i & dst_rdy_o)? ~data_i[33] : active;
+
assign data_o = data_i;
assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i;
@@ -16,13 +17,13 @@ module valve36
always @(posedge clk)
if(reset | clear)
active <= 0;
- else if(src_rdy_i & dst_rdy_o)
- active <= ~data_i[33];
+ else
+ active <= active_next;
always @(posedge clk)
if(reset | clear)
shutoff_int <= 0;
- else if(~active)
+ else if(~active_next)
shutoff_int <= shutoff;
endmodule // valve36