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authorMatt Ettus <matt@ettus.com>2010-05-11 16:11:22 -0700
committerMatt Ettus <matt@ettus.com>2010-05-11 16:11:22 -0700
commitadb82d257e28cc675d6d1ce537cfe339a9ec7092 (patch)
treef70c84f1a3789050dd6cdb709a8be14f5f4a37a9
parentc1db109e05034e7bb1e813b8d6c965cf01619aa8 (diff)
parent9df5aa38bb1cd289e80ca817c4cd7412b1eb7e0c (diff)
downloaduhd-adb82d257e28cc675d6d1ce537cfe339a9ec7092.tar.gz
uhd-adb82d257e28cc675d6d1ce537cfe339a9ec7092.tar.bz2
uhd-adb82d257e28cc675d6d1ce537cfe339a9ec7092.zip
Merge branch 'master' into udp
Diffstat
-rw-r--r--usrp2/control_lib/settings_bus.v18
-rw-r--r--usrp2/control_lib/settings_bus_crossclock.v20
-rw-r--r--usrp2/coregen/fifo_xlnx_16x40_2clk.ngc3
-rw-r--r--usrp2/coregen/fifo_xlnx_16x40_2clk.v165
-rw-r--r--usrp2/coregen/fifo_xlnx_16x40_2clk.veo51
-rw-r--r--usrp2/coregen/fifo_xlnx_16x40_2clk.xco82
-rw-r--r--usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt98
-rw-r--r--usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt8
-rw-r--r--usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt39
-rw-r--r--usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl68
-rw-r--r--usrp2/top/u2_core/u2_core.v2
11 files changed, 540 insertions, 14 deletions
diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v
index d01a30ab4..aec179516 100644
--- a/usrp2/control_lib/settings_bus.v
+++ b/usrp2/control_lib/settings_bus.v
@@ -10,8 +10,7 @@ module settings_bus
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
- input sys_clk,
- output strobe,
+ output reg strobe,
output reg [7:0] addr,
output reg [31:0] data);
@@ -20,18 +19,18 @@ module settings_bus
always @(posedge wb_clk)
if(wb_rst)
begin
- stb_int <= 1'b0;
+ strobe <= 1'b0;
addr <= 8'd0;
data <= 32'd0;
end
- else if(wb_we_i & wb_stb_i)
+ else if(wb_we_i & wb_stb_i & ~wb_ack_o)
begin
- stb_int <= 1'b1;
+ strobe <= 1'b1;
addr <= wb_adr_i[9:2];
data <= wb_dat_i;
end
else
- stb_int <= 1'b0;
+ strobe <= 1'b0;
always @(posedge wb_clk)
if(wb_rst)
@@ -39,11 +38,4 @@ module settings_bus
else
wb_ack_o <= wb_stb_i & ~wb_ack_o;
- always @(posedge wb_clk)
- stb_int_d1 <= stb_int;
-
- //assign strobe = stb_int & ~stb_int_d1;
- assign strobe = stb_int & wb_ack_o;
-
endmodule // settings_bus
-
diff --git a/usrp2/control_lib/settings_bus_crossclock.v b/usrp2/control_lib/settings_bus_crossclock.v
new file mode 100644
index 000000000..b043aa0ad
--- /dev/null
+++ b/usrp2/control_lib/settings_bus_crossclock.v
@@ -0,0 +1,20 @@
+
+
+// This module takes the settings bus on one clock domain and crosses it over to another domain
+// Typically it will be used with the input settings bus on the wishbone clock, and either
+// the system or dsp clock on the output side
+
+module settings_bus_crossclock
+ (input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i,
+ input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o);
+
+ wire full, empty;
+
+ fifo_xlnx_16x40_2clk settings_fifo
+ (.rst(rst_i),
+ .wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full),
+ .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(~empty), .empty(empty));
+
+ assign set_stb_o = ~empty;
+
+endmodule // settings_bus_crossclock
diff --git a/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc b/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc
new file mode 100644
index 000000000..f42663419
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_16x40_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$2604g<,[o}e~g`n;"2*413&;$>"9 > %10?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file
diff --git a/usrp2/coregen/fifo_xlnx_16x40_2clk.v b/usrp2/coregen/fifo_xlnx_16x40_2clk.v
new file mode 100644
index 000000000..8a08330d5
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_16x40_2clk.v
@@ -0,0 +1,165 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2007 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating
+// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_16x40_2clk(
+ din,
+ rd_clk,
+ rd_en,
+ rst,
+ wr_clk,
+ wr_en,
+ dout,
+ empty,
+ full);
+
+
+input [39 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [39 : 0] dout;
+output empty;
+output full;
+
+// synthesis translate_off
+
+ FIFO_GENERATOR_V4_3 #(
+ .C_COMMON_CLOCK(0),
+ .C_COUNT_TYPE(0),
+ .C_DATA_COUNT_WIDTH(4),
+ .C_DEFAULT_VALUE("BlankString"),
+ .C_DIN_WIDTH(40),
+ .C_DOUT_RST_VAL("0"),
+ .C_DOUT_WIDTH(40),
+ .C_ENABLE_RLOCS(0),
+ .C_FAMILY("spartan3"),
+ .C_FULL_FLAGS_RST_VAL(1),
+ .C_HAS_ALMOST_EMPTY(0),
+ .C_HAS_ALMOST_FULL(0),
+ .C_HAS_BACKUP(0),
+ .C_HAS_DATA_COUNT(0),
+ .C_HAS_INT_CLK(0),
+ .C_HAS_MEMINIT_FILE(0),
+ .C_HAS_OVERFLOW(0),
+ .C_HAS_RD_DATA_COUNT(0),
+ .C_HAS_RD_RST(0),
+ .C_HAS_RST(1),
+ .C_HAS_SRST(0),
+ .C_HAS_UNDERFLOW(0),
+ .C_HAS_VALID(0),
+ .C_HAS_WR_ACK(0),
+ .C_HAS_WR_DATA_COUNT(0),
+ .C_HAS_WR_RST(0),
+ .C_IMPLEMENTATION_TYPE(2),
+ .C_INIT_WR_PNTR_VAL(0),
+ .C_MEMORY_TYPE(2),
+ .C_MIF_FILE_NAME("BlankString"),
+ .C_MSGON_VAL(1),
+ .C_OPTIMIZATION_MODE(0),
+ .C_OVERFLOW_LOW(0),
+ .C_PRELOAD_LATENCY(0),
+ .C_PRELOAD_REGS(1),
+ .C_PRIM_FIFO_TYPE("512x72"),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+ .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+ .C_PROG_EMPTY_TYPE(0),
+ .C_PROG_FULL_THRESH_ASSERT_VAL(15),
+ .C_PROG_FULL_THRESH_NEGATE_VAL(14),
+ .C_PROG_FULL_TYPE(0),
+ .C_RD_DATA_COUNT_WIDTH(4),
+ .C_RD_DEPTH(16),
+ .C_RD_FREQ(1),
+ .C_RD_PNTR_WIDTH(4),
+ .C_UNDERFLOW_LOW(0),
+ .C_USE_DOUT_RST(1),
+ .C_USE_ECC(0),
+ .C_USE_EMBEDDED_REG(0),
+ .C_USE_FIFO16_FLAGS(0),
+ .C_USE_FWFT_DATA_COUNT(0),
+ .C_VALID_LOW(0),
+ .C_WR_ACK_LOW(0),
+ .C_WR_DATA_COUNT_WIDTH(4),
+ .C_WR_DEPTH(16),
+ .C_WR_FREQ(1),
+ .C_WR_PNTR_WIDTH(4),
+ .C_WR_RESPONSE_LATENCY(1))
+ inst (
+ .DIN(din),
+ .RD_CLK(rd_clk),
+ .RD_EN(rd_en),
+ .RST(rst),
+ .WR_CLK(wr_clk),
+ .WR_EN(wr_en),
+ .DOUT(dout),
+ .EMPTY(empty),
+ .FULL(full),
+ .CLK(),
+ .INT_CLK(),
+ .BACKUP(),
+ .BACKUP_MARKER(),
+ .PROG_EMPTY_THRESH(),
+ .PROG_EMPTY_THRESH_ASSERT(),
+ .PROG_EMPTY_THRESH_NEGATE(),
+ .PROG_FULL_THRESH(),
+ .PROG_FULL_THRESH_ASSERT(),
+ .PROG_FULL_THRESH_NEGATE(),
+ .RD_RST(),
+ .SRST(),
+ .WR_RST(),
+ .ALMOST_EMPTY(),
+ .ALMOST_FULL(),
+ .DATA_COUNT(),
+ .OVERFLOW(),
+ .PROG_EMPTY(),
+ .PROG_FULL(),
+ .VALID(),
+ .RD_DATA_COUNT(),
+ .UNDERFLOW(),
+ .WR_ACK(),
+ .WR_DATA_COUNT(),
+ .SBITERR(),
+ .DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/usrp2/coregen/fifo_xlnx_16x40_2clk.veo b/usrp2/coregen/fifo_xlnx_16x40_2clk.veo
new file mode 100644
index 000000000..684078e58
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_16x40_2clk.veo
@@ -0,0 +1,51 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2007 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_16x40_2clk YourInstanceName (
+ .din(din), // Bus [39 : 0]
+ .rd_clk(rd_clk),
+ .rd_en(rd_en),
+ .rst(rst),
+ .wr_clk(wr_clk),
+ .wr_en(wr_en),
+ .dout(dout), // Bus [39 : 0]
+ .empty(empty),
+ .full(full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_16x40_2clk.v when simulating
+// the core, fifo_xlnx_16x40_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/usrp2/coregen/fifo_xlnx_16x40_2clk.xco b/usrp2/coregen/fifo_xlnx_16x40_2clk.xco
new file mode 100644
index 000000000..d0da5a6e8
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_16x40_2clk.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Tue May 11 20:27:53 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.3
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_16x40_2clk
+CSET data_count=false
+CSET data_count_width=4
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=15
+CSET full_threshold_negate_value=14
+CSET input_data_width=40
+CSET input_depth=16
+CSET output_data_width=40
+CSET output_depth=16
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=4
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=4
+# END Parameters
+GENERATE
+# CRC: 6bcb05e1
+
diff --git a/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
new file mode 100644
index 000000000..544bda31d
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
@@ -0,0 +1,98 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="10.1.03">
+
+ <!--The data in this file is primarily intended for consumption by Xilinx tools.
+ The structure and the elements are likely to change over the next few releases.
+ This means code written to parse this file will need to be revisited each subsequent release.-->
+
+ <application stringID="Xst" timeStamp="Tue May 11 13:27:35 2010">
+ <section stringID="XST_HDL_SYNTHESIS_REPORT">
+ <item dataType="int" stringID="XST_RAMS" value="1"></item>
+ <item dataType="int" stringID="XST_COUNTERS" value="2">
+ <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
+ </item>
+ <item dataType="int" stringID="XST_REGISTERS" value="30">
+ <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
+ <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
+ <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+ <item dataType="int" stringID="XST_4BIT_REGISTER" value="11"/>
+ </item>
+ <item dataType="int" stringID="XST_XORS" value="28">
+ <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
+ </item>
+ </section>
+ <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+ <item dataType="int" stringID="XST_FSMS" value="1"/>
+ <item dataType="int" stringID="XST_RAMS" value="1"></item>
+ <item dataType="int" stringID="XST_COUNTERS" value="2">
+ <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
+ </item>
+ <item dataType="int" stringID="XST_REGISTERS" value="144">
+ <item dataType="int" stringID="XST_FLIPFLOPS" value="144"/>
+ </item>
+ <item dataType="int" stringID="XST_XORS" value="28">
+ <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
+ </item>
+ </section>
+ <section stringID="XST_FINAL_REGISTER_REPORT">
+ <item dataType="int" stringID="XST_REGISTERS" value="150">
+ <item dataType="int" stringID="XST_FLIPFLOPS" value="150"/>
+ </item>
+ </section>
+ <section stringID="XST_PARTITION_REPORT">
+ <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+ <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+ </section>
+ </section>
+ <section stringID="XST_FINAL_REPORT">
+ <section stringID="XST_FINAL_RESULTS">
+ <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc"/>
+ <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+ <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
+ <item stringID="XST_KEEP_HIERARCHY" value="no"/>
+ </section>
+ <section stringID="XST_DESIGN_STATISTICS">
+ <item stringID="XST_IOS" value="140"/>
+ </section>
+ <section stringID="XST_CELL_USAGE">
+ <item dataType="int" stringID="XST_BELS" value="42">
+ <item dataType="int" stringID="XST_GND" value="1"/>
+ <item dataType="int" stringID="XST_INV" value="2"/>
+ <item dataType="int" stringID="XST_LUT2" value="14"/>
+ <item dataType="int" stringID="XST_LUT3" value="7"/>
+ <item dataType="int" stringID="XST_LUT4" value="16"/>
+ <item dataType="int" stringID="XST_LUT4L" value="2"/>
+ </item>
+ <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="150">
+ <item dataType="int" stringID="XST_FD" value="4"/>
+ <item dataType="int" stringID="XST_FDC" value="34"/>
+ <item dataType="int" stringID="XST_FDCE" value="97"/>
+ <item dataType="int" stringID="XST_FDP" value="10"/>
+ <item dataType="int" stringID="XST_FDPE" value="5"/>
+ </item>
+ <item dataType="int" stringID="XST_RAMS" value="40">
+ <item dataType="int" stringID="XST_RAM16X1D" value="40"/>
+ </item>
+ </section>
+ </section>
+ <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+ <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
+ <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="127"/>
+ <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="150"/>
+ <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="121"/>
+ <item dataType="int" stringID="XST_NUMBER_USED_AS_LOGIC" value="41"/>
+ <item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="80"/>
+ <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="140"/>
+ <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
+ </section>
+ <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+ <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+ </section>
+ <section stringID="XST_ERRORS_STATISTICS">
+ <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+ <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="74"/>
+ <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="9"/>
+ </section>
+ </application>
+
+</document>
diff --git a/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt b/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt
new file mode 100644
index 000000000..c38f4e991
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_16x40_2clk_flist.txt
@@ -0,0 +1,8 @@
+# Output products list for <fifo_xlnx_16x40_2clk>
+fifo_xlnx_16x40_2clk.ngc
+fifo_xlnx_16x40_2clk.v
+fifo_xlnx_16x40_2clk.veo
+fifo_xlnx_16x40_2clk.xco
+fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+fifo_xlnx_16x40_2clk_flist.txt
+fifo_xlnx_16x40_2clk_xmdf.tcl
diff --git a/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt b/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt
new file mode 100644
index 000000000..bbcd4af79
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_16x40_2clk_readme.txt
@@ -0,0 +1,39 @@
+The following files were generated for 'fifo_xlnx_16x40_2clk' in directory
+/home/matt/sourcerepo/fpga/usrp2/coregen/:
+
+fifo_xlnx_16x40_2clk.ngc:
+ Binary Xilinx implementation netlist file containing the information
+ required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_16x40_2clk.v:
+ Verilog wrapper file provided to support functional simulation.
+ This file contains simulation model customization data that is
+ passed to a parameterized simulation model for the core.
+
+fifo_xlnx_16x40_2clk.veo:
+ VEO template file containing code that can be used as a model for
+ instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_16x40_2clk.xco:
+ CORE Generator input file containing the parameters used to
+ regenerate a core.
+
+fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+ Please see the core data sheet.
+
+fifo_xlnx_16x40_2clk_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+fifo_xlnx_16x40_2clk_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+fifo_xlnx_16x40_2clk_xmdf.tcl:
+ ISE Project Navigator interface file. ISE uses this file to determine
+ how the files output by CORE Generator for the core can be integrated
+ into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl b/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl
new file mode 100644
index 000000000..2b4824831
--- /dev/null
+++ b/usrp2/coregen/fifo_xlnx_16x40_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_16x40_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_16x40_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x40_2clk
+}
+# ::fifo_xlnx_16x40_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_16x40_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x40_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x40_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v
index cd0199005..2302f59ee 100644
--- a/usrp2/top/u2_core/u2_core.v
+++ b/usrp2/top/u2_core/u2_core.v
@@ -476,7 +476,7 @@ module u2_core
settings_bus settings_bus
(.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
.wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
- .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+ .strobe(set_stb),.addr(set_addr),.data(set_data));
assign s7_dat_i = 32'd0;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 21:43:10 +0000