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| author | Matt Ettus <matt@ettus.com> | 2010-12-21 13:27:12 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-12-21 13:27:12 -0800 |
| commit | 6dbdffd226139b3a780f3894a46b844869956571 (patch) | |
| tree | d259b1da8eefdbb4269052f215f3020810b7347a | |
| parent | abe10a16e3654eeac3195b344f703ce6f2fa542e (diff) | |
| download | uhd-6dbdffd226139b3a780f3894a46b844869956571.tar.gz uhd-6dbdffd226139b3a780f3894a46b844869956571.tar.bz2 uhd-6dbdffd226139b3a780f3894a46b844869956571.zip | |
don't overwrite checksum values
| -rw-r--r-- | usrp2/udp/prot_eng_tx.v | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index b86a9950c..76250029c 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -7,7 +7,8 @@ // Odd means the last word is half full // Flags[1:0] is {eop, sop} // Protocol word format is: -// 20 UDP Port Here +// 21 UDP Source Port Here +// 20 UDP Dest Port Here // 19 Last Header Line // 18 IP Header Checksum XOR // 17 IP Length Here @@ -43,7 +44,7 @@ module prot_eng_tx wire [HDR_WIDTH-1:0] header_word; reg [1:0] port_sel; - reg [32:0] per_port_data[0:3]; + reg [31:0] per_port_data[0:3]; reg [15:0] udp_src_port, udp_dst_port, chk_precompute; always @(posedge clk) udp_src_port <= per_port_data[port_sel][31:16]; @@ -51,11 +52,11 @@ module prot_eng_tx always @(posedge clk) if(set_stb & ((set_addr & 8'hE0) == BASE)) - begin - header_ram[set_addr[4:0]] <= set_data; - if(set_data[18]) - chk_precompute <= set_data[15:0]; - end + header_ram[set_addr[4:0]] <= set_data; + + always @(posedge clk) + if(set_stb & ((set_addr[4:0] & 8'hE0) == (BASE + 14))) + chk_precompute <= set_data[15:0]; always @(posedge clk) if(set_stb & ((set_addr & 8'hFC) == (BASE+24))) |