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authorMatt Ettus <matt@ettus.com>2010-08-25 18:22:44 -0700
committerMatt Ettus <matt@ettus.com>2010-08-25 18:22:44 -0700
commit5583e21ae6ff5832d4bdd935f42b4b13f1ad683a (patch)
tree4b8044e3be49dfe2b3b259d9b40fb6d40e931088
parentd0815967a27d01059230679e2d635377ac8c18b3 (diff)
parent9fa6105a49f41e39321438086b00ab12d8437828 (diff)
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Merge branch 'tx_policy' into u2p_txpolicy
* tx_policy: (21 commits) clean up DAC inversion and swapping to match schematics Clean up iq swapping on RX. It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future rx error context packets should not be marked as errors in the fifo added compat number to usrp2 readback mux makefile dependency fix for second expansion provide a way to get out of the error state without processor intervention sequence number reset upon programming streamid attempt at avoiding infinite error messages implemented "next packet" and "next burst" policies sequence errors can happen on start of burst as well. more informative error codes cleaner error handling introduce new error types test mux and gen_context_pkt this is an output file, it shouldn't be checked in insert protocol engine flags when requested move the streamid so it isn't at the same address as clear_state connect the demux fix a typo tx error packets now muxed into the ethernet stream back to the host ...
Diffstat
-rw-r--r--usrp2/fifo/fifo36_mux.v2
-rw-r--r--usrp2/fifo/fifo_new_tb.vcd5506
-rw-r--r--usrp2/fifo/fifo_tb.v25
-rw-r--r--usrp2/sdr_lib/dsp_core_rx.v35
-rw-r--r--usrp2/top/Makefile.common2
-rw-r--r--usrp2/top/u2_rev3/u2_core_udp.v56
-rw-r--r--usrp2/top/u2_rev3/u2_rev3.v15
-rw-r--r--usrp2/vrt/Makefile.srcs2
-rw-r--r--usrp2/vrt/gen_context_pkt.v72
-rw-r--r--usrp2/vrt/vita_rx_framer.v2
-rw-r--r--usrp2/vrt/vita_tx_chain.v71
-rw-r--r--usrp2/vrt/vita_tx_control.v115
-rw-r--r--usrp2/vrt/vita_tx_deframer.v30
13 files changed, 333 insertions, 5600 deletions
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v
index 04ec5abe8..92bf13ff9 100644
--- a/usrp2/fifo/fifo36_mux.v
+++ b/usrp2/fifo/fifo36_mux.v
@@ -52,6 +52,6 @@ module fifo36_mux
assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0;
assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0;
assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
- assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i;
+ assign data_o = (state==MUX_DATA0) ? data0_i : data1_i;
endmodule // fifo36_demux
diff --git a/usrp2/fifo/fifo_new_tb.vcd b/usrp2/fifo/fifo_new_tb.vcd
deleted file mode 100644
index 796889e7d..000000000
--- a/usrp2/fifo/fifo_new_tb.vcd
+++ /dev/null
@@ -1,5506 +0,0 @@
-$date
- Thu Mar 19 17:21:11 2009
-$end
-$version
- Icarus Verilog
-$end
-$timescale
- 1ps
-$end
-$scope module fifo_new_tb $end
-$var wire 1 ! dst_rdy_f36i $end
-$var wire 36 " f36_in [35:0] $end
-$var wire 36 # i1 [35:0] $end
-$var wire 1 $ i1_dr $end
-$var wire 1 % i1_sr $end
-$var wire 19 & i2 [18:0] $end
-$var wire 1 ' i2_dr $end
-$var wire 1 ( i2_sr $end
-$var wire 19 ) i3 [18:0] $end
-$var wire 1 * i3_dr $end
-$var wire 1 + i3_sr $end
-$var wire 36 , i4 [35:0] $end
-$var wire 1 - i4_sr $end
-$var wire 8 . ll_data [7:0] $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 2 ll_src_rdy_n $end
-$var reg 1 3 clear $end
-$var reg 1 4 clk $end
-$var reg 16 5 count [15:0] $end
-$var reg 1 6 dst_rdy_f36o $end
-$var reg 32 7 f36_data [31:0] $end
-$var reg 1 8 f36_eof $end
-$var reg 2 9 f36_occ [1:0] $end
-$var reg 1 : f36_sof $end
-$var reg 1 ; i4_dr $end
-$var reg 1 < rst $end
-$var reg 1 = src_rdy_f36i $end
-$scope module fifo_short1 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 36 @ datain [35:0] $end
-$var wire 36 A dataout [35:0] $end
-$var wire 1 $ dst_rdy_i $end
-$var wire 1 ! dst_rdy_o $end
-$var wire 1 B read $end
-$var wire 1 C reset $end
-$var wire 1 D src_rdy_i $end
-$var wire 1 % src_rdy_o $end
-$var wire 1 E write $end
-$var reg 4 F a [3:0] $end
-$var reg 1 G empty $end
-$var reg 1 H full $end
-$var reg 5 I occupied [4:0] $end
-$var reg 5 J space [4:0] $end
-$scope begin gen_srl16[0] $end
-$scope module srl16e $end
-$var wire 1 K A0 $end
-$var wire 1 L A1 $end
-$var wire 1 M A2 $end
-$var wire 1 N A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 O D $end
-$var wire 1 P Q $end
-$var reg 16 Q data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[1] $end
-$scope module srl16e $end
-$var wire 1 R A0 $end
-$var wire 1 S A1 $end
-$var wire 1 T A2 $end
-$var wire 1 U A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 V D $end
-$var wire 1 W Q $end
-$var reg 16 X data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[2] $end
-$scope module srl16e $end
-$var wire 1 Y A0 $end
-$var wire 1 Z A1 $end
-$var wire 1 [ A2 $end
-$var wire 1 \ A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 ] D $end
-$var wire 1 ^ Q $end
-$var reg 16 _ data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[3] $end
-$scope module srl16e $end
-$var wire 1 ` A0 $end
-$var wire 1 a A1 $end
-$var wire 1 b A2 $end
-$var wire 1 c A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 d D $end
-$var wire 1 e Q $end
-$var reg 16 f data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[4] $end
-$scope module srl16e $end
-$var wire 1 g A0 $end
-$var wire 1 h A1 $end
-$var wire 1 i A2 $end
-$var wire 1 j A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 k D $end
-$var wire 1 l Q $end
-$var reg 16 m data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[5] $end
-$scope module srl16e $end
-$var wire 1 n A0 $end
-$var wire 1 o A1 $end
-$var wire 1 p A2 $end
-$var wire 1 q A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 r D $end
-$var wire 1 s Q $end
-$var reg 16 t data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[6] $end
-$scope module srl16e $end
-$var wire 1 u A0 $end
-$var wire 1 v A1 $end
-$var wire 1 w A2 $end
-$var wire 1 x A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 y D $end
-$var wire 1 z Q $end
-$var reg 16 { data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[7] $end
-$scope module srl16e $end
-$var wire 1 | A0 $end
-$var wire 1 } A1 $end
-$var wire 1 ~ A2 $end
-$var wire 1 !" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 "" D $end
-$var wire 1 #" Q $end
-$var reg 16 $" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[8] $end
-$scope module srl16e $end
-$var wire 1 %" A0 $end
-$var wire 1 &" A1 $end
-$var wire 1 '" A2 $end
-$var wire 1 (" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 )" D $end
-$var wire 1 *" Q $end
-$var reg 16 +" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[9] $end
-$scope module srl16e $end
-$var wire 1 ," A0 $end
-$var wire 1 -" A1 $end
-$var wire 1 ." A2 $end
-$var wire 1 /" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 0" D $end
-$var wire 1 1" Q $end
-$var reg 16 2" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[10] $end
-$scope module srl16e $end
-$var wire 1 3" A0 $end
-$var wire 1 4" A1 $end
-$var wire 1 5" A2 $end
-$var wire 1 6" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 7" D $end
-$var wire 1 8" Q $end
-$var reg 16 9" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[11] $end
-$scope module srl16e $end
-$var wire 1 :" A0 $end
-$var wire 1 ;" A1 $end
-$var wire 1 <" A2 $end
-$var wire 1 =" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 >" D $end
-$var wire 1 ?" Q $end
-$var reg 16 @" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[12] $end
-$scope module srl16e $end
-$var wire 1 A" A0 $end
-$var wire 1 B" A1 $end
-$var wire 1 C" A2 $end
-$var wire 1 D" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 E" D $end
-$var wire 1 F" Q $end
-$var reg 16 G" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[13] $end
-$scope module srl16e $end
-$var wire 1 H" A0 $end
-$var wire 1 I" A1 $end
-$var wire 1 J" A2 $end
-$var wire 1 K" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 L" D $end
-$var wire 1 M" Q $end
-$var reg 16 N" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[14] $end
-$scope module srl16e $end
-$var wire 1 O" A0 $end
-$var wire 1 P" A1 $end
-$var wire 1 Q" A2 $end
-$var wire 1 R" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 S" D $end
-$var wire 1 T" Q $end
-$var reg 16 U" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[15] $end
-$scope module srl16e $end
-$var wire 1 V" A0 $end
-$var wire 1 W" A1 $end
-$var wire 1 X" A2 $end
-$var wire 1 Y" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 Z" D $end
-$var wire 1 [" Q $end
-$var reg 16 \" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[16] $end
-$scope module srl16e $end
-$var wire 1 ]" A0 $end
-$var wire 1 ^" A1 $end
-$var wire 1 _" A2 $end
-$var wire 1 `" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 a" D $end
-$var wire 1 b" Q $end
-$var reg 16 c" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[17] $end
-$scope module srl16e $end
-$var wire 1 d" A0 $end
-$var wire 1 e" A1 $end
-$var wire 1 f" A2 $end
-$var wire 1 g" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 h" D $end
-$var wire 1 i" Q $end
-$var reg 16 j" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[18] $end
-$scope module srl16e $end
-$var wire 1 k" A0 $end
-$var wire 1 l" A1 $end
-$var wire 1 m" A2 $end
-$var wire 1 n" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 o" D $end
-$var wire 1 p" Q $end
-$var reg 16 q" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[19] $end
-$scope module srl16e $end
-$var wire 1 r" A0 $end
-$var wire 1 s" A1 $end
-$var wire 1 t" A2 $end
-$var wire 1 u" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 v" D $end
-$var wire 1 w" Q $end
-$var reg 16 x" data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[20] $end
-$scope module srl16e $end
-$var wire 1 y" A0 $end
-$var wire 1 z" A1 $end
-$var wire 1 {" A2 $end
-$var wire 1 |" A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 }" D $end
-$var wire 1 ~" Q $end
-$var reg 16 !# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[21] $end
-$scope module srl16e $end
-$var wire 1 "# A0 $end
-$var wire 1 ## A1 $end
-$var wire 1 $# A2 $end
-$var wire 1 %# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 &# D $end
-$var wire 1 '# Q $end
-$var reg 16 (# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[22] $end
-$scope module srl16e $end
-$var wire 1 )# A0 $end
-$var wire 1 *# A1 $end
-$var wire 1 +# A2 $end
-$var wire 1 ,# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 -# D $end
-$var wire 1 .# Q $end
-$var reg 16 /# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[23] $end
-$scope module srl16e $end
-$var wire 1 0# A0 $end
-$var wire 1 1# A1 $end
-$var wire 1 2# A2 $end
-$var wire 1 3# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 4# D $end
-$var wire 1 5# Q $end
-$var reg 16 6# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[24] $end
-$scope module srl16e $end
-$var wire 1 7# A0 $end
-$var wire 1 8# A1 $end
-$var wire 1 9# A2 $end
-$var wire 1 :# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 ;# D $end
-$var wire 1 <# Q $end
-$var reg 16 =# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[25] $end
-$scope module srl16e $end
-$var wire 1 ># A0 $end
-$var wire 1 ?# A1 $end
-$var wire 1 @# A2 $end
-$var wire 1 A# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 B# D $end
-$var wire 1 C# Q $end
-$var reg 16 D# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[26] $end
-$scope module srl16e $end
-$var wire 1 E# A0 $end
-$var wire 1 F# A1 $end
-$var wire 1 G# A2 $end
-$var wire 1 H# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 I# D $end
-$var wire 1 J# Q $end
-$var reg 16 K# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[27] $end
-$scope module srl16e $end
-$var wire 1 L# A0 $end
-$var wire 1 M# A1 $end
-$var wire 1 N# A2 $end
-$var wire 1 O# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 P# D $end
-$var wire 1 Q# Q $end
-$var reg 16 R# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[28] $end
-$scope module srl16e $end
-$var wire 1 S# A0 $end
-$var wire 1 T# A1 $end
-$var wire 1 U# A2 $end
-$var wire 1 V# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 W# D $end
-$var wire 1 X# Q $end
-$var reg 16 Y# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[29] $end
-$scope module srl16e $end
-$var wire 1 Z# A0 $end
-$var wire 1 [# A1 $end
-$var wire 1 \# A2 $end
-$var wire 1 ]# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 ^# D $end
-$var wire 1 _# Q $end
-$var reg 16 `# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[30] $end
-$scope module srl16e $end
-$var wire 1 a# A0 $end
-$var wire 1 b# A1 $end
-$var wire 1 c# A2 $end
-$var wire 1 d# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 e# D $end
-$var wire 1 f# Q $end
-$var reg 16 g# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[31] $end
-$scope module srl16e $end
-$var wire 1 h# A0 $end
-$var wire 1 i# A1 $end
-$var wire 1 j# A2 $end
-$var wire 1 k# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 l# D $end
-$var wire 1 m# Q $end
-$var reg 16 n# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[32] $end
-$scope module srl16e $end
-$var wire 1 o# A0 $end
-$var wire 1 p# A1 $end
-$var wire 1 q# A2 $end
-$var wire 1 r# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 s# D $end
-$var wire 1 t# Q $end
-$var reg 16 u# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[33] $end
-$scope module srl16e $end
-$var wire 1 v# A0 $end
-$var wire 1 w# A1 $end
-$var wire 1 x# A2 $end
-$var wire 1 y# A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 z# D $end
-$var wire 1 {# Q $end
-$var reg 16 |# data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[34] $end
-$scope module srl16e $end
-$var wire 1 }# A0 $end
-$var wire 1 ~# A1 $end
-$var wire 1 !$ A2 $end
-$var wire 1 "$ A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 #$ D $end
-$var wire 1 $$ Q $end
-$var reg 16 %$ data [15:0] $end
-$upscope $end
-$upscope $end
-$scope begin gen_srl16[35] $end
-$scope module srl16e $end
-$var wire 1 &$ A0 $end
-$var wire 1 '$ A1 $end
-$var wire 1 ($ A2 $end
-$var wire 1 )$ A3 $end
-$var wire 1 E CE $end
-$var wire 1 ? CLK $end
-$var wire 1 *$ D $end
-$var wire 1 +$ Q $end
-$var reg 16 ,$ data [15:0] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope module fifo36_to_fifo19 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 -$ f19_dataout [18:0] $end
-$var wire 1 ' f19_dst_rdy_i $end
-$var wire 1 ( f19_src_rdy_o $end
-$var wire 1 .$ f19_xfer $end
-$var wire 36 /$ f36_datain [35:0] $end
-$var wire 1 $ f36_dst_rdy_o $end
-$var wire 1 0$ f36_eof $end
-$var wire 1 1$ f36_occ $end
-$var wire 1 2$ f36_sof $end
-$var wire 1 % f36_src_rdy_i $end
-$var wire 1 3$ f36_xfer $end
-$var wire 1 4$ half_line $end
-$var wire 1 C reset $end
-$var reg 1 5$ phase $end
-$upscope $end
-$scope module fifo19_to_ll8 $end
-$var wire 1 6$ advance $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 7$ f19_data [18:0] $end
-$var wire 1 ' f19_dst_rdy_o $end
-$var wire 1 8$ f19_eof $end
-$var wire 1 9$ f19_occ $end
-$var wire 1 :$ f19_sof $end
-$var wire 1 ( f19_src_rdy_i $end
-$var wire 1 ;$ ll_dst_rdy $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 <$ ll_eof $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 =$ ll_sof $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 >$ ll_src_rdy $end
-$var wire 1 2 ll_src_rdy_n $end
-$var wire 1 C reset $end
-$var reg 8 ?$ ll_data [7:0] $end
-$var reg 1 @$ state $end
-$upscope $end
-$scope module ll8_to_fifo19 $end
-$var wire 1 > clear $end
-$var wire 1 ? clk $end
-$var wire 19 A$ f19_data [18:0] $end
-$var wire 1 * f19_dst_rdy_i $end
-$var wire 1 + f19_src_rdy_o $end
-$var wire 8 B$ ll_data [7:0] $end
-$var wire 1 C$ ll_dst_rdy $end
-$var wire 1 / ll_dst_rdy_n $end
-$var wire 1 D$ ll_eof $end
-$var wire 1 0 ll_eof_n $end
-$var wire 1 E$ ll_sof $end
-$var wire 1 1 ll_sof_n $end
-$var wire 1 F$ ll_src_rdy $end
-$var wire 1 2 ll_src_rdy_n $end
-$var wire 1 C reset $end
-$var wire 1 G$ xfer_out $end
-$var reg 8 H$ dat0 [7:0] $end
-$var reg 8 I$ dat1 [7:0] $end
-$var reg 1 J$ f19_eof $end
-$var reg 1 K$ f19_occ $end
-$var reg 1 L$ f19_sof $end
-$var reg 2 M$ state [1:0] $end
-$upscope $end
-$scope module fifo19_to_fifo36 $end
-$var wire 1 > clear $end
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diff --git a/usrp2/fifo/fifo_tb.v b/usrp2/fifo/fifo_tb.v
index f561df7fa..327da4700 100644
--- a/usrp2/fifo/fifo_tb.v
+++ b/usrp2/fifo/fifo_tb.v
@@ -24,20 +24,39 @@ module fifo_new_tb();
wire i1_sr, i1_dr;
wire i2_sr, i2_dr;
wire i3_sr, i3_dr;
+ wire i7_sr, i7_dr;
+
reg i4_dr = 0;
wire i4_sr;
- wire [35:0] i1, i4;
+ wire [35:0] i1, i4, i7;
wire [18:0] i2, i3;
wire [7:0] ll_data;
wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+ wire [35:0] err_dat;
+ wire err_src_rdy, err_dst_rdy;
+
+ reg trigger = 0;
+ initial #10000 trigger = 1;
fifo_short #(.WIDTH(36)) fifo_short1
(.clk(clk),.reset(rst),.clear(clear),
.datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
- .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+ .dataout(i7),.src_rdy_o(i7_sr),.dst_rdy_i(i7_dr) );
+ gen_context_pkt #(.PROT_ENG_FLAGS(1)) gcp
+ (.clk(clk),.reset(rst),.clear(clear),
+ .trigger(trigger), .sent(),
+ .streamid(32'hDEAD_F00D), .vita_time(64'h01234567_89ABCDEF), .message(32'hBEEF_2940),
+ .data_o(err_dat), .src_rdy_o(err_src_rdy), .dst_rdy_i(err_dst_rdy));
+
+ fifo36_mux #(.prio(0)) fifo36_mux
+ (.clk(clk), .reset(rst), .clear(clear),
+ .data0_i(i7), .src0_rdy_i(i7_sr), .dst0_rdy_o(i7_dr),
+ .data1_i(err_dat), .src1_rdy_i(err_src_rdy), .dst1_rdy_o(err_dst_rdy),
+ .data_o(i1), .src_rdy_o(i1_sr), .dst_rdy_i(i1_dr));
+
fifo36_to_fifo19 fifo36_to_fifo19
(.clk(clk),.reset(rst),.clear(clear),
.f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
@@ -59,7 +78,7 @@ module fifo_new_tb();
(.clk(clk),.reset(rst),.clear(clear),
.f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
.f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-
+
task ReadFromFIFO36;
begin
$display("Read from FIFO36");
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 1e689fc7f..1318809d6 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -57,41 +57,32 @@ module dsp_core_rx
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_in(adc_b),.adc_out(adc_b_ofs));
- wire [3:0] muxctrl;
- setting_reg #(.my_addr(BASE+5)) sr_8
+ wire [7:0] muxctrl;
+ setting_reg #(.my_addr(BASE+5), .width(8)) sr_8
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({UNUSED_2,muxctrl}),.changed());
wire [1:0] gpio_ena;
- setting_reg #(.my_addr(BASE+6)) sr_9
+ setting_reg #(.my_addr(BASE+6), .width(2)) sr_9
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({UNUSED_3,gpio_ena}),.changed());
- // The TVRX connects to what is called adc_b, thus A and B are
- // swapped throughout the design.
- //
- // In the interest of expediency and keeping the s/w sane, we just remap them here.
- // The I & Q fields are mapped the same:
- // 0 -> "the real A" (as determined by the TVRX)
- // 1 -> "the real B"
- // 2 -> const zero
-
always @(posedge clk)
- case(muxctrl[1:0]) // The I mapping
- 0: adc_i <= adc_b_ofs; // "the real A"
- 1: adc_i <= adc_a_ofs;
+ case(muxctrl[3:0]) // The I mapping
+ 0: adc_i <= adc_a_ofs;
+ 1: adc_i <= adc_b_ofs;
2: adc_i <= 0;
default: adc_i <= 0;
- endcase // case(muxctrl[1:0])
-
+ endcase // case (muxctrl[3:0])
+
always @(posedge clk)
- case(muxctrl[3:2]) // The Q mapping
- 0: adc_q <= adc_b_ofs; // "the real A"
- 1: adc_q <= adc_a_ofs;
+ case(muxctrl[7:4]) // The Q mapping
+ 0: adc_q <= adc_a_ofs;
+ 1: adc_q <= adc_b_ofs;
2: adc_q <= 0;
default: adc_q <= 0;
- endcase // case(muxctrl[3:2])
-
+ endcase // case (muxctrl[7:4])
+
always @(posedge clk)
if(rst)
phase <= 0;
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
index 0e08b800e..1114c731e 100644
--- a/usrp2/top/Makefile.common
+++ b/usrp2/top/Makefile.common
@@ -50,7 +50,7 @@ $(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST)
@echo $@
$(ISE_HELPER) ""
-$(BIN_FILE): $(ISE_FILE)
+$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST)
@echo $@
$(ISE_HELPER) "Generate Programming File"
touch $@
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index b034791a7..c9502898b 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -423,7 +423,10 @@ module u2_core
cycle_count <= 0;
else
cycle_count <= cycle_count + 1;
-
+
+ //compatibility number -> increment when the fpga has been sufficiently altered
+ localparam compat_num = 32'd2;
+
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
.wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
@@ -431,7 +434,7 @@ module u2_core
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
- .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
+ .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count)
);
// /////////////////////////////////////////////////////////////////////////
@@ -466,11 +469,20 @@ module u2_core
.tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
.debug(debug_udp) );
+ wire [35:0] tx_err_data, udp1_tx_data;
+ wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy;
+
fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
- .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+ .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy));
+ fifo36_mux #(.prio(0)) mux_err_stream
+ (.clk(dsp_clk), .reset(dsp_reset), .clear(0),
+ .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy),
+ .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+ .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+
fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
@@ -639,40 +651,26 @@ module u2_core
// DSP TX
wire [35:0] tx_data;
- wire [99:0] tx1_data;
- wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy;
-
- wire [31:0] debug_vtc, debug_vtd, debug_vt;
+ wire tx_src_rdy, tx_dst_rdy;
+ wire [31:0] debug_vt;
fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
- vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
- .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
- .debug(debug_vtd) );
-
- vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
- (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
- .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .vita_time(vita_time),.underrun(underrun),
- .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
- .debug(debug_vtc) );
-
- assign debug_vt = debug_vtc | debug_vtd;
-
- dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
- (.clk(dsp_clk),.rst(dsp_rst),
+ vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP),
+ .REPORT_ERROR(1), .PROT_ENG_FLAGS(1))
+ vita_tx_chain
+ (.clk(dsp_clk), .reset(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
- .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .vita_time(vita_time),
+ .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+ .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
.dac_a(dac_a),.dac_b(dac_b),
- .debug(debug_tx_dsp) );
-
+ .underrun(underrun), .run(run_tx),
+ .debug(debug_vt));
+
assign dsp_rst = wb_rst;
// ///////////////////////////////////////////////////////////////////////////////////
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 3a43e4ffe..4daa66212 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -203,12 +203,13 @@ module u2_rev3
reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+ // ADC A and B are swapped in schematic to facilitate clean layout
always @(posedge dsp_clk)
begin
- adc_a_reg1 <= adc_a;
- adc_b_reg1 <= adc_b;
- adc_ovf_a_reg1 <= adc_ovf_a;
- adc_ovf_b_reg1 <= adc_ovf_b;
+ adc_a_reg1 <= adc_b;
+ adc_b_reg1 <= adc_a;
+ adc_ovf_a_reg1 <= adc_ovf_b;
+ adc_ovf_b_reg1 <= adc_ovf_a;
end
always @(posedge dsp_clk)
@@ -327,8 +328,10 @@ module u2_rev3
end
wire [15:0] dac_a_int, dac_b_int;
- always @(negedge dsp_clk) dac_a <= dac_a_int;
- always @(negedge dsp_clk) dac_b <= dac_b_int;
+ // DAC A and B are swapped in schematic to facilitate clean layout
+ // DAC A is also inverted in schematic to facilitate clean layout
+ always @(negedge dsp_clk) dac_a <= ~dac_b_int;
+ always @(negedge dsp_clk) dac_b <= dac_a_int;
/*
OFDDRRSE OFDDRRSE_serdes_inst
diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs
index 07c62224b..dc4bd8c96 100644
--- a/usrp2/vrt/Makefile.srcs
+++ b/usrp2/vrt/Makefile.srcs
@@ -10,4 +10,6 @@ vita_rx_control.v \
vita_rx_framer.v \
vita_tx_control.v \
vita_tx_deframer.v \
+vita_tx_chain.v \
+gen_context_pkt.v \
))
diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v
new file mode 100644
index 000000000..780a027ba
--- /dev/null
+++ b/usrp2/vrt/gen_context_pkt.v
@@ -0,0 +1,72 @@
+
+
+module gen_context_pkt
+ #(parameter PROT_ENG_FLAGS=1)
+ (input clk, input reset, input clear,
+ input trigger, output sent,
+ input [31:0] streamid,
+ input [63:0] vita_time,
+ input [31:0] message,
+ output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+ localparam CTXT_IDLE = 0;
+ localparam CTXT_PROT_ENG = 1;
+ localparam CTXT_HEADER = 2;
+ localparam CTXT_STREAMID = 3;
+ localparam CTXT_SECS = 4;
+ localparam CTXT_TICS = 5;
+ localparam CTXT_TICS2 = 6;
+ localparam CTXT_MESSAGE = 7;
+ localparam CTXT_DONE = 8;
+
+ reg [33:0] data_int;
+ wire src_rdy_int, dst_rdy_int;
+ wire [3:0] seqno = 0;
+ reg [3:0] ctxt_state;
+ reg [63:0] err_time;
+
+ always @(posedge clk)
+ if(reset | clear)
+ ctxt_state <= CTXT_IDLE;
+ else
+ case(ctxt_state)
+ CTXT_IDLE :
+ if(trigger)
+ begin
+ err_time <= vita_time;
+ if(PROT_ENG_FLAGS)
+ ctxt_state <= CTXT_PROT_ENG;
+ else
+ ctxt_state <= CTXT_HEADER;
+ end
+
+ CTXT_DONE :
+ if(~trigger)
+ ctxt_state <= CTXT_IDLE;
+
+ default :
+ if(dst_rdy_int)
+ ctxt_state <= ctxt_state + 1;
+ endcase // case (ctxt_state)
+
+ assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) );
+
+ always @*
+ case(ctxt_state)
+ CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd24 };
+ CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd6 };
+ CTXT_STREAMID : data_int <= { 2'b00, streamid };
+ CTXT_SECS : data_int <= { 2'b00, err_time[63:32] };
+ CTXT_TICS : data_int <= { 2'b00, 32'd0 };
+ CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] };
+ CTXT_MESSAGE : data_int <= { 2'b10, message };
+ default : data_int <= {2'b00, 32'b00};
+ endcase // case (ctxt_state)
+
+ fifo_short #(.WIDTH(34)) ctxt_fifo
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
+ .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+ assign data_o[35:34] = 2'b00;
+
+endmodule // gen_context_pkt
diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index fd82263d0..235817941 100644
--- a/usrp2/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
@@ -128,7 +128,7 @@ module vita_rx_framer
VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
- VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b11,28'd0,flags_fifo_o};
+ VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o};
//VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
new file mode 100644
index 000000000..662cdca62
--- /dev/null
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -0,0 +1,71 @@
+
+module vita_tx_chain
+ #(parameter BASE_CTRL=0,
+ parameter BASE_DSP=0,
+ parameter REPORT_ERROR=0,
+ parameter PROT_ENG_FLAGS=0)
+ (input clk, input reset,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ input [63:0] vita_time,
+ input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
+ output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i,
+ output [15:0] dac_a, output [15:0] dac_b,
+ output underrun, output run,
+ output [31:0] debug);
+
+ localparam MAXCHAN = 1;
+ localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
+
+ wire [FIFOWIDTH-1:0] tx1_data;
+ wire tx1_src_rdy, tx1_dst_rdy;
+ wire clear_vita;
+ wire [31:0] sample_tx;
+ wire [31:0] streamid, message;
+ wire trigger, sent;
+ wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp;
+
+ wire error;
+ wire [31:0] error_code;
+ wire clear_seqnum;
+
+ assign underrun = error;
+ assign message = error_code;
+
+ setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid
+ (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(streamid),.changed(clear_seqnum));
+
+ vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer
+ (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
+ .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
+ .debug(debug_vtd) );
+
+ vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control
+ (.clk(clk), .reset(reset), .clear(clear_vita),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .vita_time(vita_time),.error(error),.error_code(error_code),
+ .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
+ .sample(sample_tx), .run(run), .strobe(strobe_tx),
+ .debug(debug_vtc) );
+
+ dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx
+ (.clk(clk),.rst(reset),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .sample(sample_tx), .run(run), .strobe(strobe_tx),
+ .dac_a(dac_a),.dac_b(dac_b),
+ .debug(debug_tx_dsp) );
+
+ generate
+ if(REPORT_ERROR==1)
+ gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
+ (.clk(clk), .reset(reset), .clear(clear_vita),
+ .trigger(error), .sent(),
+ .streamid(streamid), .vita_time(vita_time), .message(message),
+ .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i));
+ endgenerate
+
+ assign debug = debug_vtc | debug_vtd;
+
+endmodule // vita_tx_chain
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index bffc64e52..d0516bec8 100644
--- a/usrp2/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
@@ -6,10 +6,11 @@ module vita_tx_control
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [63:0] vita_time,
- output underrun,
+ output error,
+ output reg [31:0] error_code,
// From vita_tx_deframer
- input [4+64+WIDTH-1:0] sample_fifo_i,
+ input [5+64+16+WIDTH-1:0] sample_fifo_i,
input sample_fifo_src_rdy_i,
output sample_fifo_dst_rdy_o,
@@ -20,14 +21,17 @@ module vita_tx_control
output [31:0] debug
);
-
- assign sample = sample_fifo_i[4+64+WIDTH-1:4+64];
+
+ assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16];
wire [63:0] send_time = sample_fifo_i[63:0];
- wire eop = sample_fifo_i[64];
- wire eob = sample_fifo_i[65];
- wire sob = sample_fifo_i[66];
- wire send_at = sample_fifo_i[67];
+ wire [15:0] seqnum = sample_fifo_i[79:64];
+ wire eop = sample_fifo_i[80];
+ wire eob = sample_fifo_i[81];
+ wire sob = sample_fifo_i[82];
+ wire send_at = sample_fifo_i[83];
+ wire seqnum_err = sample_fifo_i[84];
+
wire now, early, late, too_early;
// FIXME ignore too_early for now for timing reasons
@@ -40,8 +44,15 @@ module vita_tx_control
localparam IBS_IDLE = 0;
localparam IBS_RUN = 1; // FIXME do we need this?
localparam IBS_CONT_BURST = 2;
- localparam IBS_UNDERRUN = 3;
- localparam IBS_UNDERRUN_DONE = 4;
+ localparam IBS_ERROR = 3;
+ localparam IBS_ERROR_DONE = 4;
+ localparam IBS_ERROR_WAIT = 5;
+
+ wire [31:0] CODE_UNDERRUN = {seqnum,16'd2};
+ wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4};
+ wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8};
+ wire [31:0] CODE_UNDERRUN_MIDPKT = {seqnum,16'd16};
+ wire [31:0] CODE_SEQ_ERROR_MIDBURST = {seqnum,16'd32};
reg [2:0] ibs_state;
@@ -50,22 +61,49 @@ module vita_tx_control
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_state));
+ wire [31:0] error_policy;
+ setting_reg #(.my_addr(BASE+3)) sr_error_policy
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(error_policy),.changed());
+
+ wire policy_wait = error_policy[0];
+ wire policy_next_packet = error_policy[1];
+ wire policy_next_burst = error_policy[2];
+ reg send_error;
+
always @(posedge clk)
if(reset | clear_state)
- ibs_state <= 0;
+ begin
+ ibs_state <= IBS_IDLE;
+ send_error <= 0;
+ end
else
case(ibs_state)
IBS_IDLE :
if(sample_fifo_src_rdy_i)
- if(~send_at | now)
+ if(seqnum_err)
+ begin
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_SEQ_ERROR;
+ send_error <= 1;
+ end
+ else if(~send_at | now)
ibs_state <= IBS_RUN;
else if(late | too_early)
- ibs_state <= IBS_UNDERRUN;
+ begin
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_TIME_ERROR;
+ send_error <= 1;
+ end
IBS_RUN :
if(strobe)
if(~sample_fifo_src_rdy_i)
- ibs_state <= IBS_UNDERRUN;
+ begin
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_UNDERRUN_MIDPKT;
+ send_error <= 1;
+ end
else if(eop)
if(eob)
ibs_state <= IBS_IDLE;
@@ -74,24 +112,53 @@ module vita_tx_control
IBS_CONT_BURST :
if(strobe)
- ibs_state <= IBS_UNDERRUN_DONE;
+ begin
+ if(policy_next_packet)
+ ibs_state <= IBS_ERROR_DONE;
+ else if(policy_wait)
+ ibs_state <= IBS_ERROR_WAIT;
+ else
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_UNDERRUN;
+ send_error <= 1;
+ end
else if(sample_fifo_src_rdy_i)
- ibs_state <= IBS_RUN;
+ if(seqnum_err)
+ begin
+ ibs_state <= IBS_ERROR;
+ error_code <= CODE_SEQ_ERROR_MIDBURST;
+ send_error <= 1;
+ end
+ else
+ ibs_state <= IBS_RUN;
- IBS_UNDERRUN :
- if(sample_fifo_src_rdy_i & eop)
- ibs_state <= IBS_UNDERRUN_DONE;
+ IBS_ERROR :
+ begin
+ send_error <= 0;
+ if(sample_fifo_src_rdy_i & eop)
+ if(policy_next_packet | (policy_next_burst & eob))
+ ibs_state <= IBS_IDLE;
+ else if(policy_wait)
+ ibs_state <= IBS_ERROR_WAIT;
+ end
- IBS_UNDERRUN_DONE :
- ;
+ IBS_ERROR_DONE :
+ begin
+ send_error <= 0;
+ ibs_state <= IBS_IDLE;
+ end
+
+ IBS_ERROR_WAIT :
+ send_error <= 0;
endcase // case (ibs_state)
- assign sample_fifo_dst_rdy_o = (ibs_state == IBS_UNDERRUN) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout
+ assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout
assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
- assign underrun = (ibs_state == IBS_UNDERRUN_DONE);
+ //assign error = (ibs_state == IBS_ERROR_DONE);
+ assign error = send_error;
assign debug = { { now,early,late,too_early,eop,eob,sob,send_at },
- { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, underrun, ibs_state[2:0] },
+ { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] },
{ 8'b0 },
{ 8'b0 } };
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index 3b95f5902..f9cd7d00d 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -2,7 +2,7 @@
module vita_tx_deframer
#(parameter BASE=0,
parameter MAXCHAN=1)
- (input clk, input reset, input clear,
+ (input clk, input reset, input clear, input clear_seqnum,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
// To FIFO interface of Buffer Pool
@@ -10,7 +10,7 @@ module vita_tx_deframer
input src_rdy_i,
output dst_rdy_o,
- output [4+64+(32*MAXCHAN)-1:0] sample_fifo_o,
+ output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o,
output sample_fifo_src_rdy_o,
input sample_fifo_dst_rdy_i,
@@ -21,6 +21,8 @@ module vita_tx_deframer
output [31:0] debug
);
+ localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
+
wire [1:0] numchan;
setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
@@ -36,14 +38,18 @@ module vita_tx_deframer
assign is_sob = data_i[25];
assign is_eob = data_i[24];
wire eof = data_i[33];
-
reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg;
reg has_trailer_reg, is_sob_reg, is_eob_reg;
-
+
reg [15:0] pkt_len;
reg [1:0] vector_phase;
wire line_done;
+ reg seqnum_err;
+ reg [3:0] seqnum_reg;
+ wire [3:0] seqnum = data_i[19:16];
+ wire [3:0] next_seqnum = seqnum_reg + 4'd1;
+
// Output FIFO for packetized data
localparam VITA_HEADER = 0;
localparam VITA_STREAMID = 1;
@@ -61,6 +67,13 @@ module vita_tx_deframer
wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets?
wire fifo_space;
+
+ always @(posedge clk)
+ if(reset | clear_seqnum)
+ seqnum_reg <= 4'hF;
+ else
+ if((vita_state==VITA_HEADER) & src_rdy_i)
+ seqnum_reg <= seqnum;
always @(posedge clk)
if(reset | clear)
@@ -68,6 +81,7 @@ module vita_tx_deframer
vita_state <= VITA_HEADER;
{has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg}
<= 0;
+ seqnum_err <= 0;
end
else
if((vita_state == VITA_STORE) & fifo_space)
@@ -99,6 +113,7 @@ module vita_tx_deframer
vita_state <= VITA_TICS;
else
vita_state <= VITA_PAYLOAD;
+ seqnum_err <= ~(seqnum == next_seqnum);
end // case: VITA_HEADER
VITA_STREAMID :
if(has_classid_reg)
@@ -145,7 +160,7 @@ module vita_tx_deframer
assign line_done = (vector_phase == numchan);
- wire [4+64+32*MAXCHAN-1:0] fifo_i;
+ wire [FIFOWIDTH-1:0] fifo_i;
reg [63:0] send_time;
reg [31:0] sample_a, sample_b, sample_c, sample_d;
@@ -169,13 +184,14 @@ module vita_tx_deframer
endcase // case (vector_phase)
wire store = (vita_state == VITA_STORE);
- fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q
+ fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q
(.clk(clk), .reset(reset), .clear(clear),
.datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space),
.dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) );
// sob, eob, has_secs (send_at) ignored on all lines except first
- assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time};
+ assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop,
+ 12'd0,seqnum_reg,send_time};
assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 21:48:23 +0000