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| author | Matt Ettus <matt@ettus.com> | 2011-04-22 15:17:36 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:22 -0700 |
| commit | 42561353c372696337983e74a5c7b690afa2aedd (patch) | |
| tree | 5fd07829149406720ff3d07da206a1f1393e471e | |
| parent | 08149d4c4e904d3a224ac9e24814ce04f3d9c509 (diff) | |
| download | uhd-42561353c372696337983e74a5c7b690afa2aedd.tar.gz uhd-42561353c372696337983e74a5c7b690afa2aedd.tar.bz2 uhd-42561353c372696337983e74a5c7b690afa2aedd.zip | |
u1p: reset gpif
| -rw-r--r-- | usrp2/gpif/packet_splitter_tb.v | 4 | ||||
| -rw-r--r-- | usrp2/top/u1plus/u1plus_core.v | 6 |
2 files changed, 6 insertions, 4 deletions
diff --git a/usrp2/gpif/packet_splitter_tb.v b/usrp2/gpif/packet_splitter_tb.v index d35f1c6d4..877f6ae1c 100644 --- a/usrp2/gpif/packet_splitter_tb.v +++ b/usrp2/gpif/packet_splitter_tb.v @@ -33,7 +33,7 @@ module packet_splitter_tb(); vita_pkt_gen vita_pkt_gen (.clk(sys_clk), .reset(sys_rst) , .clear(0), - .len(7),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); + .len(512),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); fifo36_to_fifo19 #(.LE(1)) f36_to_f19 (.clk(sys_clk), .reset(sys_rst), .clear(0), @@ -42,7 +42,7 @@ module packet_splitter_tb(); packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter (.clk(sys_clk), .reset(sys_rst), .clear(0), - .frames_per_packet(3), + .frames_per_packet(4), .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index a2147e463..26565afa6 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -53,6 +53,8 @@ module u1plus_core wire [31:0] debug1; wire [31:0] debug_vt; + wire gpif_rst; + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; reg [7:0] frames_per_packet; @@ -63,7 +65,8 @@ module u1plus_core (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(global_reset)); - reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); wire [15:0] test_len; // ///////////////////////////////////////////////////////////////////////////////////// @@ -84,7 +87,6 @@ module u1plus_core tx_err_src_rdy, tx_err_dst_rdy; wire bus_error; - wire gpif_rst = 0; wire clear_tx, clear_rx; setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx |