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| author | Matt Ettus <matt@ettus.com> | 2010-07-20 11:16:41 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-20 11:16:41 -0700 |
| commit | 3b6b6e153084bf1d57231c0a565e2a0204467b04 (patch) | |
| tree | bf3477baf704605eefae74fb4482604f6b040b1e | |
| parent | e73ffa9f830b070a6b897edfbcfadf35b6b1f0c6 (diff) | |
| download | uhd-3b6b6e153084bf1d57231c0a565e2a0204467b04.tar.gz uhd-3b6b6e153084bf1d57231c0a565e2a0204467b04.tar.bz2 uhd-3b6b6e153084bf1d57231c0a565e2a0204467b04.zip | |
connect SPI to adc, correct capitalization of SEN pins
| -rw-r--r-- | usrp2/top/u2plus/u2plus.v | 17 | ||||
| -rw-r--r-- | usrp2/top/u2plus/u2plus_core.v | 3 |
2 files changed, 11 insertions, 9 deletions
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index 1feed1314..efa1c9390 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -346,14 +346,15 @@ module u2plus .sclk (sclk_int), .mosi (mosi), .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), + .sen_clk (SEN_CLK), + .sen_dac (SEN_DAC), + .sen_adc (SEN_ADC), + .sen_tx_db (SEN_TX_DB), + .sen_tx_adc (SEN_TX_ADC), + .sen_tx_dac (SEN_TX_DAC), + .sen_rx_db (SEN_RX_DB), + .sen_rx_adc (SEN_RX_ADC), + .sen_rx_dac (SEN_RX_DAC), .io_tx (io_tx[15:0]), .io_rx (io_rx[15:0]), .RAM_D (RAM_D), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 9e197cfbb..b71b34e8d 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -97,6 +97,7 @@ module u2plus_core input miso, output sen_clk, output sen_dac, + output sen_adc, output sen_tx_db, output sen_tx_adc, output sen_tx_dac, @@ -375,7 +376,7 @@ defparam bootram.RAM0.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_ (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .ss_pad_o({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); // ///////////////////////////////////////////////////////////////////////// |