U2P: 32/64Mbit FLASH support, internal reference support for U2P r2

4 files changed, 30 insertions, 18 deletions

diff --git a/firmware/microblaze/usrp2p/bootloader_utils.h b/firmware/microblaze/usrp2p/bootloader_utils.h
index c72128f43..f597c0113 100644
--- a/firmware/microblaze/usrp2p/bootloader_utils.h
+++ b/firmware/microblaze/usrp2p/bootloader_utils.h
@@ -7,14 +7,15 @@
 #include <stdint.h>
 
 //we're working in bytes and byte addresses so we can run the same code with Flash chips of different sector sizes.
-#define FPGA_IMAGE_SIZE_BYTES 2097152
+//it's really 1463736, but rounded up to 1.5MB
+#define FPGA_IMAGE_SIZE_BYTES 1572864
 //instead of 32K, we write 31K because we're using the top 1K for stack space!
 #define FW_IMAGE_SIZE_BYTES 31744
 
 #define SAFE_FPGA_IMAGE_LOCATION_ADDR 0x00000000
-#define SAFE_FW_IMAGE_LOCATION_ADDR 0x007F0000
-#define PROD_FPGA_IMAGE_LOCATION_ADDR 0x00200000
-#define PROD_FW_IMAGE_LOCATION_ADDR 0x00400000
+#define SAFE_FW_IMAGE_LOCATION_ADDR 0x003F0000
+#define PROD_FPGA_IMAGE_LOCATION_ADDR 0x00180000
+#define PROD_FW_IMAGE_LOCATION_ADDR 0x00300000
 
 int is_valid_fpga_image(uint32_t addr);
 int is_valid_fw_image(uint32_t addr);
diff --git a/host/lib/ic_reg_maps/CMakeLists.txt b/host/lib/ic_reg_maps/CMakeLists.txt
index 507f214c9..772166334 100644
--- a/host/lib/ic_reg_maps/CMakeLists.txt
+++ b/host/lib/ic_reg_maps/CMakeLists.txt
@@ -70,11 +70,11 @@ LIBUHD_PYTHON_GEN_SOURCE(
 )
 
 LIBUHD_PYTHON_GEN_SOURCE(
-<<<<<<< HEAD
     ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_ads62p44_regs.py
     ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/ads62p44_regs.hpp
-=======
+    )
+
+LIBUHD_PYTHON_GEN_SOURCE(
     ${CMAKE_SOURCE_DIR}/lib/ic_reg_maps/gen_tuner_4937di5_regs.py
     ${CMAKE_BINARY_DIR}/lib/ic_reg_maps/tuner_4937di5_regs.hpp
->>>>>>> bd3bd0dfbc1a87af5839c9b23450434cfb9c763c
 )
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 2669df9bc..3ae21e621 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -160,11 +160,21 @@ void usrp2_mboard_impl::update_clock_config(void){
     _iface->poke32(_iface->regs.time64_flags, pps_flags);
 
     //clock source ref 10mhz
-    switch(_clock_config.ref_source){
-    case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x10); break;
-    case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break;
-    case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break;
-    default: throw std::runtime_error("usrp2: unhandled clock configuration reference source");
+    if(_iface->get_hw_rev() >= USRP2P_FIRST_HW_REV) {
+        switch(_clock_config.ref_source){
+        case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x12); break;
+        case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break;
+        case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break;
+        default: throw std::runtime_error("usrp2: unhandled clock configuration reference source");
+        }
+    } else {
+    
+        switch(_clock_config.ref_source){
+        case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x10); break;
+        case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break;
+        case clock_config_t::REF_MIMO: _iface->poke32(_iface->regs.misc_ctrl_clock, 0x15); break;
+        default: throw std::runtime_error("usrp2: unhandled clock configuration reference source");
+        }
     }
 
     //clock source ref 10mhz
diff --git a/host/utils/usrp2p_fw_update.py b/host/utils/usrp2p_fw_update.py
index 5eff83c07..ed3465c0e 100755
--- a/host/utils/usrp2p_fw_update.py
+++ b/host/utils/usrp2p_fw_update.py
@@ -39,12 +39,13 @@ UDP_POLL_INTERVAL = 0.10 #in seconds
 USRP2_FW_PROTO_VERSION = 6
 
 #from bootloader_utils.h
-PROD_FPGA_IMAGE_LOCATION_ADDR = 0x00200000
-PROD_FW_IMAGE_LOCATION_ADDR   = 0x00400000
-SAFE_FW_IMAGE_LOCATION_ADDR   = 0x007F0000
-SAFE_FPGA_IMAGE_LOCATION_ADDR = 0x00000000
-FPGA_IMAGE_SIZE_BYTES         = 2097152
-FW_IMAGE_SIZE_BYTES      = 31744
+
+#define FPGA_IMAGE_SIZE_BYTES 1572864
+#define FW_IMAGE_SIZE_BYTES 31744
+#define SAFE_FPGA_IMAGE_LOCATION_ADDR 0x00000000
+#define SAFE_FW_IMAGE_LOCATION_ADDR 0x003F0000
+#define PROD_FPGA_IMAGE_LOCATION_ADDR 0x00180000
+#define PROD_FW_IMAGE_LOCATION_ADDR 0x00300000
 
 FLASH_DATA_PACKET_SIZE = 256