added a loopback control port, will do full wishbone interface later

3 files changed, 50 insertions, 7 deletions

diff --git a/usrp2/control_lib/fifo_to_wb.v b/usrp2/control_lib/fifo_to_wb.v
new file mode 100644
index 000000000..fdc76f89e
--- /dev/null
+++ b/usrp2/control_lib/fifo_to_wb.v
@@ -0,0 +1,34 @@
+
+module fifo_to_wb
+  (input clk, input reset, input clear,
+   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i,
+   output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+   output wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+   output [31:0] debug0, output [31:0] debug1);
+
+   wire [35:0] 	 ctrl_data, resp_data;
+   wire 	 ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy;
+   
+   fifo_short #(.WIDTH(36)) ctrl_sfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy));
+
+   fifo_short #(.WIDTH(36)) resp_sfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy),
+      .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+   
+   // Loopback control packets
+   
+   assign resp_data = ctrl_data;
+   assign resp_src_rdy = ctrl_src_rdy;
+   assign ctrl_dst_rdy = resp_dst_rdy;
+
+   assign debug0 = ctrl_data[31:0];
+   assign debug1 = { ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_data[35:31] };
+   		  
+endmodule // fifo_to_wb
+
+   
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index bd813126f..9697a7f8b 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -17,7 +17,7 @@ module gpif
     output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
     input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
     
-    output [31:0] debug
+    output [31:0] debug0, output [31:0] debug1
     );
 
    wire 	  WR = gpif_ctl[0];
@@ -105,5 +105,12 @@ module gpif
    // ////////////////////////////////////////////////////////////////////
    // FIFO to Wishbone interface
 
+   fifo_to_wb fifo_to_wb
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy),
+      .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy),
+      .wb_adr_o(), .wb_dat_mosi(), .wb_dat_miso(),
+      .wb_sel_o(), .wb_cyc_o(), .wb_stb_o(), .wb_we_o(), .wb_ack_i(),
+      .debug0(), .debug1());
    
 endmodule // gpif
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v
index 3cdc74835..97064a561 100644
--- a/usrp2/top/u1plus/u1plus_core.v
+++ b/usrp2/top/u1plus/u1plus_core.v
@@ -54,7 +54,7 @@ module u1plus_core
    wire [sw-1:0] m0_sel;
    wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
 
-   wire [31:0] 	 debug_gpmc;
+   wire [31:0] 	 debug_gpmc, debug0, debug1;
 
    wire [35:0] 	 tx_data, rx_data;
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy;
@@ -75,7 +75,7 @@ module u1plus_core
 	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
 	 
-	 .debug(debug_gpmc));
+	 .debug0(debug0), .debug1(debug1));
 
    wire 	 rx_sof = rx_data[32];
    wire 	 rx_eof = rx_data[33];
@@ -366,14 +366,14 @@ module u1plus_core
 
    wire [31:0] 	atr_lines;
    wire [31:0] 	debug_gpio_0, debug_gpio_1;
-   
+/*   
    nsgpio16LE 
      nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst),
 		.cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
 		.dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack),
 		.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
 		.gpio( {io_tx,io_rx} ) );
-
+*/
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #5
 
@@ -403,9 +403,11 @@ module u1plus_core
    // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry
 
-   assign debug_clk = { 1'b0, clk_fpga };
-   assign debug = 0;
+   assign debug_clk = { gpif_clk, clk_fpga };
+   assign debug = debug0;
    assign debug_gpio_0 = 0;
    assign debug_gpio_1 = 0;
+
+   assign {io_tx,io_rx} = debug1;
    
 endmodule // u1plus_core