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authorMatt Ettus <matt@ettus.com>2010-02-25 19:43:01 -0800
committerMatt Ettus <matt@ettus.com>2010-02-25 19:43:01 -0800
commit67dd6732b70c1cd35a7134f4830b09b893255935 (patch)
tree2033576c9e09965558274115691e794c0cef4cad
parent9143c4a4ca2bf14b43796ae0a0508dbedc40d0e4 (diff)
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gpmc debug pins
-rw-r--r--usrp2/gpmc/gpmc.v9
-rw-r--r--usrp2/top/u1e/u1e_core.v9
2 files changed, 14 insertions, 4 deletions
diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 831df3b4c..cf1357232 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -16,7 +16,8 @@ module gpmc
// RAM Interface signals
input ram_clk,
input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done,
- input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done
+ input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done,
+ output [31:0] debug
);
wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
@@ -65,6 +66,12 @@ module gpmc
.read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out),
.write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done));
+
+ assign debug = { { 2'b00, write_done_in, write_sel_in, read_en, read_sel_in, read_ready, read_done},
+ { 2'b00, read_sel_out, write_en, write_sel_out, read_done_out, write_ready, write_done },
+ { 8'd0 },
+ { 8'd0 } };
+
// CS6 is Control, Wishbone bus bridge (wb master)
// Sync version
reg [1:0] cs_del, we_del, oe_del;
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index e14152f33..6706d4aac 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -33,6 +33,8 @@ module u1e_core
reg [8:0] addr;
wire read_done, write_done, read_en, write_en, read_ready, write_ready;
+
+ wire [31:0] debug_gpmc;
gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
@@ -49,7 +51,8 @@ module u1e_core
.read_en(read_en), .read_addr(read_addr), .read_data(read_data),
.read_ready(read_ready), .read_done(read_done),
.write_en(write_en), .write_addr(write_addr), .write_data(write_data),
- .write_ready(write_ready), .write_done(write_done) );
+ .write_ready(write_ready), .write_done(write_done),
+ .debug(debug_gpmc));
// Loopback
assign write_data = read_data;
@@ -241,10 +244,10 @@ module u1e_core
// Debug circuitry
assign debug_clk = { EM_CLK, clk_fpga };
- assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
+ assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
{ EM_D } };
- assign debug_gpio_0 = { m0_we, m0_stb, m0_ack, s1_stb, s0_stb, m0_adr[10:0], m0_dat_mosi[15:0] };
+ assign debug_gpio_0 = { debug_gpmc };
assign debug_gpio_1 = { debug_txd, debug_rxd };
assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board