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author | Josh Blum <josh@joshknows.com> | 2011-05-16 11:55:42 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-05-20 14:28:06 -0700 |
commit | 9b4fa86af2d0ed59d0881a3d153b309c94c7e4e5 (patch) | |
tree | fa7597ff68cac339823cc8e8eef56e0e2f4445be | |
parent | f58abdcba9ab23a399d7da2687e772c6ae24f41d (diff) | |
download | uhd-9b4fa86af2d0ed59d0881a3d153b309c94c7e4e5.tar.gz uhd-9b4fa86af2d0ed59d0881a3d153b309c94c7e4e5.tar.bz2 uhd-9b4fa86af2d0ed59d0881a3d153b309c94c7e4e5.zip |
u1e: incremented compat # to 4 for vita length change
-rw-r--r-- | usrp2/top/u1e/u1e_core.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 8e6d74edf..d10a3ab30 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -36,7 +36,7 @@ module u1e_core localparam SR_GLOBAL_RESET = 50; // 1 reg localparam SR_REG_TEST32 = 52; // 1 reg - wire [7:0] COMPAT_NUM = 8'd3; + wire [7:0] COMPAT_NUM = 8'd4; wire wb_clk = clk_fpga; wire wb_rst, global_reset; |