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authorMatt Ettus <matt@ettus.com>2010-04-14 18:01:28 -0700
committerMatt Ettus <matt@ettus.com>2010-04-14 18:01:28 -0700
commit8cef80c8ebb9b59f1fe65971c9066fd832ab2504 (patch)
treee7588532c2731c6f6f186c9849cf4f36118d2f0e
parent19d476df81cdf7a51b871154510be8f7c575ffde (diff)
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probably won't be using this, and it hasn't been tested
-rw-r--r--usrp2/gpmc/ram_to_fifo.v46
1 files changed, 46 insertions, 0 deletions
diff --git a/usrp2/gpmc/ram_to_fifo.v b/usrp2/gpmc/ram_to_fifo.v
new file mode 100644
index 000000000..8549dcc35
--- /dev/null
+++ b/usrp2/gpmc/ram_to_fifo.v
@@ -0,0 +1,46 @@
+
+
+module ram_to_fifo
+ (input clk, input reset,
+ input [10:0] read_length, // From the dbsm (?)
+ output read_en, output reg [8:0] read_addr, input [31:0] read_data, input read_ready, output read_done,
+ output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+ // read_length/2 = number of 32 bit lines, numbered 0 through read_length/2-1
+ wire [8:0] last_line = (read_length[10:1]-1);
+
+ reg read_phase, sop;
+
+ assign read_en = (read_phase == 0) | dst_rdy_i;
+ assign src_rdy_o = (read_phase == 1);
+
+ always @(posedge clk)
+ if(reset)
+ begin
+ read_addr <= 0;
+ read_phase <= 0;
+ sop <= 1;
+ end
+ else
+ if(read_phase == 0)
+ begin
+ read_addr <= read_ready;
+ read_phase <= read_ready;
+ end
+ else if(dst_rdy_i)
+ begin
+ sop <= 0;
+ if(read_addr == last_line)
+ begin
+ read_addr <= 0;
+ read_phase <= 0;
+ end
+ else
+ read_addr <= read_addr + 1;
+ end
+
+ assign read_done = (read_phase == 1) & (read_addr == last_line) & dst_rdy_i;
+ wire eop = (read_addr == last_line);
+ assign data_o = { 2'b00, eop, sop, read_data };
+
+endmodule // ram_to_fifo