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| author | Matt Ettus <matt@ettus.com> | 2011-01-25 11:49:37 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-01-25 11:49:37 -0800 |
| commit | 56b0c233736cf9d3d4e85668cd49e9b39a3a98e3 (patch) | |
| tree | a7e0630ac588926c735ad250b3d49f201346dc8d | |
| parent | 2d6a8bf01a664ce3edef269c2835e587e9b1e714 (diff) | |
| download | uhd-56b0c233736cf9d3d4e85668cd49e9b39a3a98e3.tar.gz uhd-56b0c233736cf9d3d4e85668cd49e9b39a3a98e3.tar.bz2 uhd-56b0c233736cf9d3d4e85668cd49e9b39a3a98e3.zip | |
reorganized u1e register space to make room for 64 settingregs
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index d590b4fb1..2dad1e169 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -29,12 +29,13 @@ module u1e_core localparam TXFIFOSIZE = 13; localparam RXFIFOSIZE = 13; - localparam SR_RX_DSP = 0; // 5 regs - localparam SR_CLEAR_FIFO = 6; // 1 reg - localparam SR_RX_CTRL = 8; // 9 regs - localparam SR_TX_DSP = 17; // 5 regs - localparam SR_TX_CTRL = 24; // 2 regs - localparam SR_TIME64 = 28; // 4 regs + // 64 total regs in address space + localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) + localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) + localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) + localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) + localparam SR_TIME64 = 40; // 6 regs (+0 to +5) + localparam SR_CLEAR_FIFO = 48; // 1 reg wire [7:0] COMPAT_NUM = 8'd3; @@ -203,7 +204,9 @@ module u1e_core wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) + .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), + .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), + .DSP_NUMBER(0)) vita_tx_chain (.clk(wb_clk), .reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -258,7 +261,7 @@ module u1e_core .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), - .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) @@ -411,10 +414,10 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 - // only have 32 regs, 32 bits each with current setup... - settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), - .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), + // only have 64 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi), + .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); // ///////////////////////////////////////////////////////////////////////// |