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| author | Josh Blum <josh@joshknows.com> | 2010-07-29 17:26:19 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-07-29 17:26:19 -0700 |
| commit | 1cddf89b0ea0b509418ea9a817bd1cebbdfdb118 (patch) | |
| tree | 7815b28f7fe5cb883d7973f79a66c24940d45861 | |
| parent | 5f3e51f8d200d8494765fdb3bafbcfe2a3701d8f (diff) | |
| parent | 23a0454998d8904d4e6f2f3f8bc0a79557043321 (diff) | |
| download | uhd-1cddf89b0ea0b509418ea9a817bd1cebbdfdb118.tar.gz uhd-1cddf89b0ea0b509418ea9a817bd1cebbdfdb118.tar.bz2 uhd-1cddf89b0ea0b509418ea9a817bd1cebbdfdb118.zip | |
Merge branch 'tx_policy'
| -rw-r--r-- | firmware/microblaze/apps/txrx_uhd.c | 2 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/mboard_impl.cpp | 1 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 5 |
3 files changed, 7 insertions, 1 deletions
diff --git a/firmware/microblaze/apps/txrx_uhd.c b/firmware/microblaze/apps/txrx_uhd.c index f7f140121..6b45f8f3b 100644 --- a/firmware/microblaze/apps/txrx_uhd.c +++ b/firmware/microblaze/apps/txrx_uhd.c @@ -484,7 +484,7 @@ main(void) int pending = pic_regs->pending; // poll for under or overrun if (pending & PIC_UNDERRUN_INT){ - dbsm_handle_tx_underrun(&dsp_tx_sm); + //dbsm_handle_tx_underrun(&dsp_tx_sm); pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt putchar('U'); } diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index b3b03c11c..0ac988361 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -85,6 +85,7 @@ usrp2_mboard_impl::usrp2_mboard_impl( _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0); //1 channel _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1); //sid 1 (different from rx) + _iface->poke32(U2_REG_TX_CTRL_POLICY, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET); //init the ddc init_ddc_config(); diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index aa8bd860f..cc9094ae7 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -247,5 +247,10 @@ #define U2_REG_TX_CTRL_NUM_CHAN _SR_ADDR(SR_TX_CTRL + 0) #define U2_REG_TX_CTRL_CLEAR_STATE _SR_ADDR(SR_TX_CTRL + 1) #define U2_REG_TX_CTRL_REPORT_SID _SR_ADDR(SR_TX_CTRL + 2) +#define U2_REG_TX_CTRL_POLICY _SR_ADDR(SR_TX_CTRL + 3) + +#define U2_FLAG_TX_CTRL_POLICY_WAIT (0x1 << 0) +#define U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET (0x1 << 1) +#define U2_FLAG_TX_CTRL_POLICY_NEXT_BURST (0x1 << 2) #endif /* INCLUDED_USRP2_REGS_HPP */ |