vita rx instead of rx_control. Ready for firmware testing. Misses timing by a little bit, will worry later.

4 files changed, 48 insertions, 4 deletions

diff --git a/control_lib/setting_reg.v b/control_lib/setting_reg.v
index ccbaa3d2e..c8aff230f 100644
--- a/control_lib/setting_reg.v
+++ b/control_lib/setting_reg.v
@@ -1,14 +1,14 @@
 
 
 module setting_reg
-  #(parameter my_addr = 0)
+  #(parameter my_addr = 0, parameter at_reset=32'd0)
     (input clk, input rst, input strobe, input wire [7:0] addr,
      input wire [31:0] in, output reg [31:0] out, output reg changed);
    
    always @(posedge clk)
      if(rst)
        begin
-	  out <= 32'd0;
+	  out <= at_reset;
 	  changed <= 1'b0;
        end
      else
diff --git a/timing/time_compare.v b/timing/time_compare.v
new file mode 100644
index 000000000..edfa7375a
--- /dev/null
+++ b/timing/time_compare.v
@@ -0,0 +1,21 @@
+
+// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second
+
+module time_compare
+  (input [63:0] time_now,
+   input [63:0] trigger_time,
+   output now,
+   output early,
+   output late);
+   
+   wire    sec_match   = (time_now[63:32] == trigger_time[63:32]);
+   wire    sec_late    = (time_now[63:32] > trigger_time[63:32]);
+
+   wire    tick_match  = (time_now[31:0] == trigger_time[31:0]);
+   wire    tick_late   = (time_now[31:0] > trigger_time[31:0]);
+   
+   assign now 	       = sec_match & tick_match;
+   assign late 	       = sec_late | (sec_match & tick_late);
+   assign early        = ~now & ~late;
+
+endmodule // time_compare
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index 5b272c366..48440e25c 100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -136,6 +136,7 @@ module u2_core
    input [3:0] clock_divider
    );
 
+   localparam SR_RXCTRL = 160;
    localparam SR_TIME64 = 192;
    
    wire [7:0] 	set_addr;
@@ -554,6 +555,7 @@ module u2_core
    wire [31:0] 	 sample_rx, sample_tx;
    wire 	 strobe_rx, strobe_tx;
 
+   /*
    rx_control #(.FIFOSIZE(10)) rx_control
      (.clk(dsp_clk), .rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -562,8 +564,26 @@ module u2_core
       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
       .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
       .debug_rx(debug_rx) );
-   
-   // dumkmy_rx dsp_core_rx
+*/
+   vita_rx_control #(.BASE(SR_RXCTRL)) vita_rx_control
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time), .overrun(overrun),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy));
+
+   vita_rx_framer #(.BASE(SR_RXCTRL)) vita_rx_framer
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
+      .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty() );
+
+   fifo_cascade #(.WIDTH(36), .SIZE(10)) rx_fifo_cascade
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
+      .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
+
    dsp_core_rx dsp_core_rx
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
index 8b18550d1..a6fcc36f0 100644
--- a/top/u2_rev3/Makefile
+++ b/top/u2_rev3/Makefile
@@ -84,6 +84,8 @@ control_lib/wb_bridge_16_32.v \
 control_lib/reset_sync.v \
 control_lib/priority_enc.v \
 control_lib/pic.v \
+vrt/vita_rx_control.v \
+vrt/vita_rx_framer.v \
 simple_gemac/simple_gemac_wrapper.v \
 simple_gemac/simple_gemac.v \
 simple_gemac/simple_gemac_wb.v \
@@ -172,6 +174,7 @@ serdes/serdes_fc_tx.v \
 serdes/serdes_rx.v \
 serdes/serdes_tx.v \
 timing/time_64bit.v \
+timing/time_compare.v \
 timing/time_receiver.v \
 timing/time_sender.v \
 timing/time_sync.v \