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author | Matt Ettus <matt@ettus.com> | 2010-03-10 14:31:15 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2010-03-10 14:31:15 -0800 |
commit | 1a811a72c56c9abf8114d4349e53bddb573ecb86 (patch) | |
tree | 94677775e53fe90c25b2e61242692bef55ea2c27 | |
parent | e6e5c4c4797cf8e30964731d0a4c04f65488a8ec (diff) | |
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copy in wrong place
-rw-r--r-- | timing/simple_timer.v | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/timing/simple_timer.v b/timing/simple_timer.v deleted file mode 100644 index 17c7f1c36..000000000 --- a/timing/simple_timer.v +++ /dev/null @@ -1,60 +0,0 @@ - - -module simple_timer - #(parameter BASE=0) - (input clk, input reset, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - output reg onetime_int, output reg periodic_int); - - reg [31:0] onetime_ctr; - always @(posedge clk) - if(reset) - begin - onetime_int <= 0; - onetime_ctr <= 0; - end - else - if(set_stb & (set_addr == BASE)) - begin - onetime_int <= 0; - onetime_ctr <= set_data; - end - else - begin - if(onetime_ctr == 1) - onetime_int <= 1; - if(onetime_ctr != 0) - onetime_ctr <= onetime_ctr - 1; - else - onetime_int <= 0; - end // else: !if(set_stb & (set_addr == BASE)) - - reg [31:0] periodic_ctr, period; - always @(posedge clk) - if(reset) - begin - periodic_int <= 0; - periodic_ctr <= 0; - period <= 0; - end - else - if(set_stb & (set_addr == (BASE+1))) - begin - periodic_int <= 0; - periodic_ctr <= set_data; - period <= set_data; - end - else - if(periodic_ctr == 1) - begin - periodic_int <= 1; - periodic_ctr <= period; - end - else - if(periodic_ctr != 0) - begin - periodic_int <= 0; - periodic_ctr <= periodic_ctr - 1; - end - -endmodule // simple_timer |