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authorMatt Ettus <matt@ettus.com>2009-09-02 17:01:28 -0700
committerMatt Ettus <matt@ettus.com>2009-09-02 17:01:28 -0700
commitf4e4c9b99d753e477fe4151609767ef4245efd4a (patch)
tree84e760f3915a2b2040bf1422273e21c5c5775c29
parent29fa1be3dc307d6d9be0fc3a004213eea50e6071 (diff)
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sort out active-low lines on locallink fifos, added debug pins
-rw-r--r--simple_gemac/simple_gemac_wrapper.v18
1 files changed, 15 insertions, 3 deletions
diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v
index e21eafb80..31bc02ebb 100644
--- a/simple_gemac/simple_gemac_wrapper.v
+++ b/simple_gemac/simple_gemac_wrapper.v
@@ -18,7 +18,8 @@ module simple_gemac_wrapper
input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
// MIIM
- inout mdio, output mdc );
+ inout mdio, output mdc,
+ output [31:0] debug);
wire [7:0] rx_data, tx_data;
wire tx_clk, tx_valid, tx_error, tx_ack;
@@ -91,6 +92,7 @@ module simple_gemac_wrapper
// TX FIFO Chain
wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
+ wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
wire [7:0] tx_ll_data, tx_ll_data2;
wire [35:0] tx_f36_data_int1;
wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
@@ -105,12 +107,17 @@ module simple_gemac_wrapper
(.clk(tx_clk), .reset(tx_reset), .clear(clear),
.f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
.ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
- .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2));
+ .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
+
+ assign tx_ll_sof2 = ~tx_ll_sof2_n;
+ assign tx_ll_eof2 = ~tx_ll_eof2_n;
+ assign tx_ll_src_rdy2 = ~tx_ll_src_rdy2_n;
+ assign tx_ll_dst_rdy2_n = ~tx_ll_dst_rdy2;
ll8_shortfifo tx_sfifo
(.clk(rx_clk), .reset(tx_reset), .clear(clear),
.datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
- .error_i(0), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2),
+ .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
.dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
.error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
@@ -120,4 +127,9 @@ module simple_gemac_wrapper
.ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
.tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+ assign debug = { { tx_ll_data },
+ { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy,
+ tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
+ { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]},
+ { tx_data} };
endmodule // simple_gemac_wrapper