hook up under/overruns for debug purposes

2 files changed, 12 insertions, 8 deletions

diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index b2c91dfbc..38bfd3e25 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -23,7 +23,8 @@ module gpmc_async
     input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
     
     input [15:0] tx_frame_len, output [15:0] rx_frame_len,
-    
+
+    output tx_underrun, output rx_overrun,
     output [31:0] debug
     );
 
@@ -144,7 +145,6 @@ module gpmc_async
    wire [31:0] 	total, crc_err, seq_err, len_err;
    wire [7:0] 	rx_rate, tx_rate;
    wire 	rx_enable, tx_enable;
-   wire 	underrun, overrun;
    wire 	sel_testtx, sel_loopbacktx;
    
    fifo36_mux rx_test_mux_lvl_1
@@ -186,7 +186,7 @@ module gpmc_async
      (.clk(fifo_clk), .reset(fifo_rst), .rate(tx_rate), .enable(tx_enable),
       .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy),
       .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int),
-      .underrun(underrun), .overrun());
+      .underrun(tx_underrun), .overrun());
 
    packet_verifier32 pktver32
      (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
@@ -203,10 +203,10 @@ module gpmc_async
      (.clk(fifo_clk), .reset(fifo_rst), .rate(rx_rate), .enable(rx_enable),
       .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int),
       .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy),
-      .underrun(), .overrun(overrun));
+      .underrun(), .overrun(rx_overrun));
 
    // FIXME -- hook up crossbar controls
-   // FIXME -- collect error stats
+   // // FIXME -- collect error stats
    // FIXME -- set rates and enables on pacers
    // FIXME -- make sure packet completes before we shutoff
    // FIXME -- handle overrun and underrun
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 4f5a3e112..c0e92ec6c 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -50,7 +50,10 @@ module u1e_core
    wire 	set_stb;
 
    wire [31:0] 	debug_vt;
-
+   wire 	rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
+   assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp;
+   assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
+   
    setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
      (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(),.changed(global_reset));
@@ -107,6 +110,7 @@ module u1e_core
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
 	 
 	 .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+	 .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
 	 .debug(debug_gpmc));
 
    wire 	 rx_sof = rx_data[32];
@@ -135,7 +139,7 @@ module u1e_core
    vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
      (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .vita_time(vita_time), .overrun(rx_overrun),
+      .vita_time(vita_time), .overrun(rx_overrun_dsp),
       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
       .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy),
       .debug_rx(vrc_debug));
@@ -171,7 +175,7 @@ module u1e_core
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .dac_a(tx_i_int),.dac_b(tx_q_int),
-      .underrun(underrun), .run(run_tx),
+      .underrun(tx_underrun_dsp), .run(run_tx),
       .debug(debug_vt));
    
    assign tx_i = tx_i_int[15:2];