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| author | Matt Ettus <matt@ettus.com> | 2011-03-03 16:36:21 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-03 16:36:21 -0800 |
| commit | 470b20b47da7639bc29740497d1dba6f251ebd97 (patch) | |
| tree | 7ccd0a157dceaec05a247d07639b273f37e456f0 | |
| parent | 595d341ea6cd9b2207d5443bf79b144f87e9674b (diff) | |
| download | uhd-470b20b47da7639bc29740497d1dba6f251ebd97.tar.gz uhd-470b20b47da7639bc29740497d1dba6f251ebd97.tar.bz2 uhd-470b20b47da7639bc29740497d1dba6f251ebd97.zip | |
make big tx fifo the one doing the clock crossing
| -rw-r--r-- | usrp2/simple_gemac/simple_gemac_wrapper.v | 2 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 14 |
2 files changed, 4 insertions, 12 deletions
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v index 38c47ca37..cb0ec1c71 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -1,7 +1,7 @@ module simple_gemac_wrapper #(parameter RXFIFOSIZE=9, - parameter TXFIFOSIZE=6) + parameter TXFIFOSIZE=9) (input clk125, input reset, // GMII output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 17b732e78..7504efeb3 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -433,10 +433,8 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - wire [35:0] tx_f36_data; - wire tx_f36_src_rdy, tx_f36_dst_rdy; - - simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), @@ -444,18 +442,12 @@ module u2_core .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), .sys_clk(dsp_clk), .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), - .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy), + .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - //eth output to mac tx... - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rd2_dat), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); - // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus |