need to enable both 16 and 32 bit spi interfaces -- 16 used in u1e, 32 in u2 and u2p

1 files changed, 1 insertions, 0 deletions

diff --git a/usrp2/opencores/Makefile.srcs b/usrp2/opencores/Makefile.srcs
index 1ccecf337..284578b39 100644
--- a/usrp2/opencores/Makefile.srcs
+++ b/usrp2/opencores/Makefile.srcs
@@ -23,5 +23,6 @@ i2c/rtl/verilog/timescale.v \
 spi/rtl/verilog/spi_clgen.v \
 spi/rtl/verilog/spi_defines.v \
 spi/rtl/verilog/spi_shift.v \
+spi/rtl/verilog/spi_top.v \
 spi/rtl/verilog/spi_top16.v \
 ))