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| author | Philip Balister <philip@opensdr.com> | 2010-08-18 00:41:41 +0000 |
|---|---|---|
| committer | Philip Balister <philip@opensdr.com> | 2010-08-18 00:41:41 +0000 |
| commit | f7fab232e5b6124b0bda821736ac309ccc0cab94 (patch) | |
| tree | d64c163e675d27ea232aa680dd24983c343637df | |
| parent | e48dfb211609e26230c2e7c165ad3aa5d5b0ecfc (diff) | |
| download | uhd-f7fab232e5b6124b0bda821736ac309ccc0cab94.tar.gz uhd-f7fab232e5b6124b0bda821736ac309ccc0cab94.tar.bz2 uhd-f7fab232e5b6124b0bda821736ac309ccc0cab94.zip | |
Really fix TX IQ phase offset.
| -rw-r--r-- | host/lib/usrp/usrp_e/codec_ctrl.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index 45063894e..837219759 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -29,7 +29,7 @@ using namespace uhd; -static const bool codec_debug = false; +static const bool codec_debug = true; const gain_range_t usrp_e_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1)); const gain_range_t usrp_e_codec_ctrl::rx_pga_gain_range(0, 20, 1); @@ -98,7 +98,7 @@ usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; _ad9862_regs.dac_a_coarse_gain = 0x3; _ad9862_regs.dac_b_coarse_gain = 0x3; - _ad9862_regs.edges = ad9862_regs_t::EDGES_BOTH; + _ad9862_regs.edges = ad9862_regs_t::EDGES_NORMAL; //setup the dll _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; |