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| author | Matt Ettus <matt@ettus.com> | 2010-12-09 23:39:49 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-12-09 23:39:49 -0800 |
| commit | 66e1d8f94b82df3dccbe6f785c7224f0763009f3 (patch) | |
| tree | 87a06ec4235be17a531aed832f27174764387a8b | |
| parent | 3555f0498f36feae14d0bdbbe6a8ecd0db513db0 (diff) | |
| download | uhd-66e1d8f94b82df3dccbe6f785c7224f0763009f3.tar.gz uhd-66e1d8f94b82df3dccbe6f785c7224f0763009f3.tar.bz2 uhd-66e1d8f94b82df3dccbe6f785c7224f0763009f3.zip | |
udp is now the default
| -rw-r--r-- | usrp2/top/u2_rev3/Makefile.udp | 4 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v (renamed from usrp2/top/u2_rev3/u2_core_udp.v) | 0 |
2 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp index 99effb038..05ada2476 100644 --- a/usrp2/top/u2_rev3/Makefile.udp +++ b/usrp2/top/u2_rev3/Makefile.udp @@ -6,7 +6,7 @@ # Project Setup ################################################## TOP_MODULE = u2_rev3 -BUILD_DIR = $(abspath build-udp$(ISE)) +BUILD_DIR = $(abspath build) ################################################## # Include other makefiles @@ -46,7 +46,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -u2_core_udp.v \ +u2_core.v \ u2_rev3.v \ u2_rev3.ucf diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core.v index c2d473650..c2d473650 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core.v |