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| author | Paul David <paul.david@ettus.com> | 2016-09-29 14:36:04 -0700 |
|---|---|---|
| committer | mbr0wn <martin.braun@ettus.com> | 2016-10-05 14:31:53 -0700 |
| commit | ed3be5607de7ea20f3ed1a5bfef4a060ade006be (patch) | |
| tree | a5ec90c7d18bd91eb63fbe566d0980f15e8705df | |
| parent | 93990d78520848d00e586d6bae10048c36d2ea89 (diff) | |
| download | uhd-ed3be5607de7ea20f3ed1a5bfef4a060ade006be.tar.gz uhd-ed3be5607de7ea20f3ed1a5bfef4a060ade006be.tar.bz2 uhd-ed3be5607de7ea20f3ed1a5bfef4a060ade006be.zip | |
max2871: Added label for the bit region VAS_DLY
- Also added a template specialization for enabling the VAS_DLY bit locations based on VAS_TEMP setting (aka retune)
| -rwxr-xr-x | host/lib/ic_reg_maps/gen_max2871_regs.py | 5 | ||||
| -rw-r--r-- | host/lib/usrp/common/max287x.hpp | 7 |
2 files changed, 11 insertions, 1 deletions
diff --git a/host/lib/ic_reg_maps/gen_max2871_regs.py b/host/lib/ic_reg_maps/gen_max2871_regs.py index f591c1636..f500d8aa8 100755 --- a/host/lib/ic_reg_maps/gen_max2871_regs.py +++ b/host/lib/ic_reg_maps/gen_max2871_regs.py @@ -74,6 +74,7 @@ counter_reset 0x02[3] 0 normal, reset vco 0x03[26:31] 0 ## VCO autoselect shutdown_vas 0x03[25] 0 enabled, disabled +## should actually be called vas_temp ... retune 0x03[24] 1 disabled, enabled res3 0x3[19:23] 0 csm 0x3[18] 0 disabled, enabled @@ -107,7 +108,9 @@ output_power 0x04[3:4] 3 m4dBm, m1dBm, 2dBm, 5dBm ## Misc ## Write only, default = 0x18400005 ######################################################################## -res5_26_31 0x05[26:31] 0x18 +res5_31 0x05[31] 0 +vas_dly 0x05[29:30] 3 disabled, res0, res1, enabled +res5_26_28 0x05[26:28] 0 shutdown_pll 0x05[25] 0 enabled, disabled f01 0x05[24] 1 frac_n, auto ld_pin_mode 0x05[22:23] 1 low, dld, ald, high diff --git a/host/lib/usrp/common/max287x.hpp b/host/lib/usrp/common/max287x.hpp index 596d992e0..540f5207f 100644 --- a/host/lib/usrp/common/max287x.hpp +++ b/host/lib/usrp/common/max287x.hpp @@ -824,6 +824,13 @@ void max287x<max287x_regs_t>::set_auto_retune(bool enabled) _regs.retune = enabled ? max287x_regs_t::RETUNE_ENABLED : max287x_regs_t::RETUNE_DISABLED; } +template <> +inline void max287x<max2871_regs_t>::set_auto_retune(bool enabled) +{ + _regs.retune = enabled ? max2871_regs_t::RETUNE_ENABLED : max2871_regs_t::RETUNE_DISABLED; + _regs.vas_dly = enabled ? max2871_regs_t::VAS_DLY_ENABLED : max2871_regs_t::VAS_DLY_DISABLED; +} + template <typename max287x_regs_t> void max287x<max287x_regs_t>::set_clock_divider_mode(clock_divider_mode_t mode) { |