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| author | Wade Fife <wade.fife@ettus.com> | 2020-06-09 11:26:01 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-06-29 13:41:15 -0500 |
| commit | ed1b58053c53bfbd3f3b667a0ebe0aa8066e2b0e (patch) | |
| tree | 9b032346e1dd4da42c05a8de35dbcb6acd47e2cd | |
| parent | 5c1771cc68edca442d870611ef8d9662b5d00d8b (diff) | |
| download | uhd-ed1b58053c53bfbd3f3b667a0ebe0aa8066e2b0e.tar.gz uhd-ed1b58053c53bfbd3f3b667a0ebe0aa8066e2b0e.tar.bz2 uhd-ed1b58053c53bfbd3f3b667a0ebe0aa8066e2b0e.zip | |
fpga: lib: Fix axi_packet_gate RAM dib width
| -rw-r--r-- | fpga/usrp3/lib/fifo/axi_packet_gate.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/fifo/axi_packet_gate.v b/fpga/usrp3/lib/fifo/axi_packet_gate.v index 771fb2200..c0037e80f 100644 --- a/fpga/usrp3/lib/fifo/axi_packet_gate.v +++ b/fpga/usrp3/lib/fifo/axi_packet_gate.v @@ -70,7 +70,7 @@ module axi_packet_gate #( .clka (clk), .ena(1'b1), .wea(wr_en), .addra(wr_addr), .dia(wr_data), .doa(), .clkb (clk), .enb(rd_en), .web(1'b0), - .addrb(rd_addr), .dib({WIDTH{1'b0}}), .dob(rd_data) + .addrb(rd_addr), .dib({WIDTH+1{1'b0}}), .dob(rd_data) ); // FIFO empty/full logic. The condition for both |