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| author | Wade Fife <wade.fife@ettus.com> | 2020-02-14 09:47:45 -0600 |
|---|---|---|
| committer | Wade Fife <32272501+wordimont@users.noreply.github.com> | 2020-03-05 13:49:38 -0600 |
| commit | e06ff0f5e08458256bf7ffdd3d9c84c4c1046807 (patch) | |
| tree | 9c75079d7d9f6f207f0c05999f5a158f12d96610 | |
| parent | 9a45d4449fdac7b53ae5bc97b58cd09b42bfdd2a (diff) | |
| download | uhd-e06ff0f5e08458256bf7ffdd3d9c84c4c1046807.tar.gz uhd-e06ff0f5e08458256bf7ffdd3d9c84c4c1046807.tar.bz2 uhd-e06ff0f5e08458256bf7ffdd3d9c84c4c1046807.zip | |
rfnoc: Fix FIR and AXI RAM block register documentation
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.vh | 16 | ||||
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_regs.vh | 4 |
2 files changed, 11 insertions, 9 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.vh index ccb942552..3b48093b0 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.vh +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/axi_ram_fifo_regs.vh @@ -14,7 +14,7 @@ localparam RAM_FIFO_ADDR_W = 7; -// REG_FIFO_INFO (R|W) +// REG_FIFO_INFO (R) // // Contains info/control bits for the FIFO. // @@ -153,13 +153,15 @@ localparam REG_FIFO_PACKET_CNT = 'h28; // [3] : Continuous mode (run until stopped). When set to 1, test will continue // to run until Stop bit is set. // -// [2] : Clear the BIST counters (i.e., the TX, RX, cycle, and error counters) +// [2] : Clear the BIST counters (strobe). Resets the TX, RX, cycle, and error +// counters. This bit is self-clearing. // -// [1] : Stop BIST (strobe). Write a 1 to this bit to stop the test that is -// currently running +// [1] : Stop BIST (strobe). Write a 1 to this bit to stop the test that is +// currently running. This bit is self-clearing. // -// [0] : Start BIST (strobe). Write a 1 to this bit to start a test using the -// configured NUM_BYTES and continuous mode setting. +// [0] : Start BIST (strobe). Write a 1 to this bit to start a test using the +// configured NUM_BYTES and continuous mode setting. This bit is +// self-clearing. // localparam REG_BIST_CTRL = 'h30; // @@ -170,7 +172,7 @@ localparam REG_BIST_STOP_POS = 1; // Strobe localparam REG_BIST_START_POS = 0; // Strobe -// REG_BIST_CLOCK_RATE (R) +// REG_BIST_CLK_RATE (R) // // Reports the clock rate of the BIST component in Hz. This can be used with // REG_BIST_CYCLE_COUNT to calculate throughput. diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_regs.vh b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_regs.vh index 0e070e3a3..520396bf2 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_regs.vh +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_fir_filter_regs.vh @@ -24,7 +24,7 @@ localparam FIR_FILTER_ADDR_W = 4; localparam REG_FIR_NUM_COEFFS = 'h0; -// REG_FIR_LOAD_COEFF (R) +// REG_FIR_LOAD_COEFF (W) // // Register for inputting the next coefficient to be loaded into the filter. To // load a new set of filter coefficients, write NUM_COEFFS-1 coefficients to @@ -38,7 +38,7 @@ localparam REG_FIR_NUM_COEFFS = 'h0; localparam REG_FIR_LOAD_COEFF = 'h4; -// REG_FIR_LOAD_COEFF_LAST (R) +// REG_FIR_LOAD_COEFF_LAST (W) // // Register for inputting the last coefficient to be loaded into the filter. To // load a new set of filter coefficients, write NUM_COEFFS-1 coefficients to |