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authorRyan Marlow <ryan.marlow@ettus.com>2017-10-16 17:05:17 -0400
committerMartin Braun <martin.braun@ettus.com>2017-12-22 15:04:02 -0800
commitc6f228452db79982cc08a9f0af1322b8585fc90e (patch)
tree1381b3c991ffad020b7994ad53f033ce7c9366db
parent832e9fc79469ec8d95b68a6f752483718707e548 (diff)
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n3xx: enable 1G clock with gpio settings.
-rw-r--r--mpm/python/usrp_mpm/periph_manager/n310.py17
1 files changed, 17 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py
index 703ce0cf8..465e31c06 100644
--- a/mpm/python/usrp_mpm/periph_manager/n310.py
+++ b/mpm/python/usrp_mpm/periph_manager/n310.py
@@ -234,6 +234,7 @@ class n310(PeriphManagerBase):
self._gpios = TCA6424(int(self.mboard_info['rev']))
self.log.trace("Enabling power of MGT156MHZ clk")
self._gpios.set("PWREN-CLK-MGT156MHz")
+ self.enable_1G_ref_clock()
self.enable_gps(
enable=bool(
args.default_args.get('enable_gps', N3XX_DEFAULT_ENABLE_GPS)
@@ -486,6 +487,22 @@ class n310(PeriphManagerBase):
"Enabling" if enable else "Disabling"
))
self._gpios.set("PWREN-CLK-MAINREF", int(bool(enable)))
+
+ def enable_1G_ref_clock(self):
+ """
+ Enables 125 MHz refclock for 1G interface.
+ """
+ self.log.trace("Enable 125 MHz Clock for 1G SFP interface.")
+ self._gpios.set("NETCLK-CE")
+ self._gpios.set("NETCLK-RESETn", 0)
+ self._gpios.set("NETCLK-PR0", 1)
+ self._gpios.set("NETCLK-PR1", 1)
+ self._gpios.set("NETCLK-OD0", 1)
+ self._gpios.set("NETCLK-OD1", 1)
+ self._gpios.set("NETCLK-OD2", 0)
+ self._gpios.set("PWREN-CLK-WB-25MHz", 1)
+ self.log.trace("Finished configuring NETCLK CDCM.")
+ self._gpios.set("NETCLK-RESETn", 1)
###########################################################################
# Sensors