sim: Add Daughterboard Methods

This commit adds daughterboard simulation to the simulator. There is a
sim_dboard class which registers it's methods with the rpc server. These
methods are visible over mpm as well as the mpm_shell.

Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>

7 files changed, 130 insertions, 14 deletions

diff --git a/mpm/python/usrp_mpm/CMakeLists.txt b/mpm/python/usrp_mpm/CMakeLists.txt
index 93c140a8d..293892337 100644
--- a/mpm/python/usrp_mpm/CMakeLists.txt
+++ b/mpm/python/usrp_mpm/CMakeLists.txt
@@ -31,4 +31,5 @@ add_subdirectory(dboard_manager)
 add_subdirectory(periph_manager)
 add_subdirectory(sys_utils)
 add_subdirectory(xports)
+add_subdirectory(simulator)
 set(USRP_MPM_FILES ${USRP_MPM_FILES} PARENT_SCOPE)
diff --git a/mpm/python/usrp_mpm/dboard_manager/__init__.py b/mpm/python/usrp_mpm/dboard_manager/__init__.py
index 77fd84436..3677394fc 100644
--- a/mpm/python/usrp_mpm/dboard_manager/__init__.py
+++ b/mpm/python/usrp_mpm/dboard_manager/__init__.py
@@ -7,10 +7,12 @@
 dboards module __init__.py
 """
 from .base import DboardManagerBase
-from .magnesium import Magnesium
-from .rhodium import Rhodium
-from .neon import Neon
-from .e31x_db import E31x_db
-from .eiscat import EISCAT
-from .test import test
-from .unknown import unknown
+from usrp_mpm import __simulated__
+if not __simulated__:
+    from .magnesium import Magnesium
+    from .rhodium import Rhodium
+    from .neon import Neon
+    from .e31x_db import E31x_db
+    from .eiscat import EISCAT
+    from .test import test
+    from .unknown import unknown
diff --git a/mpm/python/usrp_mpm/periph_manager/sim.py b/mpm/python/usrp_mpm/periph_manager/sim.py
index 00ba5ba38..7c8baeb8f 100644
--- a/mpm/python/usrp_mpm/periph_manager/sim.py
+++ b/mpm/python/usrp_mpm/periph_manager/sim.py
@@ -6,9 +6,8 @@
 """
 usrp simulation module
 
-This module is used to emulate a usrp when running on a standard
-computer. You can build mpm in this configuration by using the cmake
-flag -DMPM_DEVICE=sim
+This module is used to emulate simulated devices. You can build mpm in this
+configuration by using the cmake flag -DMPM_DEVICE=sim
 """
 
 from pyroute2 import IPRoute
@@ -16,6 +15,7 @@ from usrp_mpm.xports import XportMgrUDP
 from usrp_mpm.mpmlog import get_logger
 from usrp_mpm.rpc_server import no_claim
 from usrp_mpm.periph_manager import PeriphManagerBase
+from usrp_mpm.simulator.sim_dboard_catalina import SimulatedCatalinaDboard
 
 CLOCK_SOURCE_INTERNAL = "internal"
 
@@ -91,6 +91,9 @@ class sim(PeriphManagerBase):
         if not args.get('skip_boot_init', False):
             self.init(args)
 
+    def _simulator_frequency(self, freq):
+        self.log.debug("Setting Simulator Sample Frequency to {}".format(freq))
+
     @classmethod
     def generate_device_info(cls, eeprom_md, mboard_info, dboard_infos):
         """
@@ -144,6 +147,10 @@ class sim(PeriphManagerBase):
         # Init complete.
         self.log.debug("Device info: {}".format(self.device_info))
 
+    def _init_dboards(self, dboard_infos, override_dboard_pids, default_args):
+        self.dboards.append(SimulatedCatalinaDboard(E320_DBOARD_SLOT_IDX, self._simulator_frequency))
+        self.log.info("Found %d daughterboard(s).", len(self.dboards))
+
     ###########################################################################
     # Device info
     ###########################################################################
@@ -218,10 +225,6 @@ class sim(PeriphManagerBase):
     #######################################################################
     # Timekeeper API
     #######################################################################
-    def get_master_clock_rate(self):
-        """ Return the master clock rate set during init """
-        return self._master_clock_rate
-
     def get_num_timekeepers(self):
         """
         Return the number of timekeepers
diff --git a/mpm/python/usrp_mpm/simulator/CMakeLists.txt b/mpm/python/usrp_mpm/simulator/CMakeLists.txt
new file mode 100644
index 000000000..6cc4ee441
--- /dev/null
+++ b/mpm/python/usrp_mpm/simulator/CMakeLists.txt
@@ -0,0 +1,18 @@
+#
+# Copyright 2020 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+
+########################################################################
+# This file included, use CMake directory variables
+########################################################################
+
+set(USRP_MPM_FILES ${USRP_MPM_FILES})
+set(USRP_MPM_SIMULATOR_FILES
+    ${CMAKE_CURRENT_SOURCE_DIR}/__init__.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/sim_dboard.py
+    ${CMAKE_CURRENT_SOURCE_DIR}/sim_dboard_catalina.py
+)
+list(APPEND USRP_MPM_FILES ${USRP_MPM_SIMULATOR_FILES})
+set(USRP_MPM_FILES ${USRP_MPM_FILES} PARENT_SCOPE)
diff --git a/mpm/python/usrp_mpm/simulator/__init__.py b/mpm/python/usrp_mpm/simulator/__init__.py
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/mpm/python/usrp_mpm/simulator/__init__.py
diff --git a/mpm/python/usrp_mpm/simulator/sim_dboard.py b/mpm/python/usrp_mpm/simulator/sim_dboard.py
new file mode 100644
index 000000000..a264eae9c
--- /dev/null
+++ b/mpm/python/usrp_mpm/simulator/sim_dboard.py
@@ -0,0 +1,59 @@
+#
+# Copyright 2020 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+from usrp_mpm.dboard_manager import DboardManagerBase
+from usrp_mpm.mpmlog import get_logger
+from usrp_mpm.mpmutils import to_native_str
+
+class SimulatedDboardBase(DboardManagerBase):
+    """
+    A class to simulate daughterboards in a simulated device.
+    """
+
+    # Extra Overridables:
+    # This is a list of extra methods to add to the class
+    # Each element should be either a string or a tuple of
+    # (string, function). Each element is added to the class
+    # with the name being the string and the function being
+    # the function, or the default of taking any amount of
+    # arguments and returning None
+    extra_methods = []
+
+    def __init__(self, slot_idx, **kwargs):
+        super().__init__(slot_idx, **kwargs)
+        self.log = get_logger("sim_db-{}".format(slot_idx))
+        self.device_info = {
+            'pid': to_native_str(self.__class__.pids[0]),
+            'serial': to_native_str("todo:serial-here"),
+            'rev': to_native_str("1"),
+            'eeprom_version': to_native_str('0')
+        }
+        self.rev = int(self.device_info['rev'])
+
+        self.log.trace("This is a rev: {}".format(chr(65 + self.rev)))
+        self._make_extra_methods()
+
+    def init(self, args):
+        self.log.trace("sim_db#init called")
+        return True
+
+    def tear_down(self):
+        self.log.trace("sim_db#tear_down called")
+
+    def _make_extra_methods(self):
+        for entry in self.__class__.extra_methods:
+            func = None
+            prop_name = None
+            if type(entry) is tuple:
+                func = entry[1]
+                prop_name = entry[0]
+            else:
+                func = lambda *args: None
+                prop_name = entry
+            # default values are needed because loop iterations don't create a new scope in python
+            def wrapped_func(*args, prop_name=prop_name, func=func):
+                self.log.debug("Called {} with args: {}".format(prop_name, args))
+                return func(*args)
+            setattr(self, prop_name, wrapped_func)
diff --git a/mpm/python/usrp_mpm/simulator/sim_dboard_catalina.py b/mpm/python/usrp_mpm/simulator/sim_dboard_catalina.py
new file mode 100644
index 000000000..4e46d1410
--- /dev/null
+++ b/mpm/python/usrp_mpm/simulator/sim_dboard_catalina.py
@@ -0,0 +1,33 @@
+#
+# Copyright 2020 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+from .sim_dboard import SimulatedDboardBase
+
+class SimulatedCatalinaDboard(SimulatedDboardBase):
+    pids = [0x0110]
+
+    extra_methods = [
+        ("set_gain", lambda target, gain: gain),
+        ("catalina_tune", lambda which, freq: freq),
+        ("set_bw_filter", lambda which, freq: freq),
+        "set_dc_offset_auto",
+        "set_iq_balance_auto",
+        "set_agc",
+        "set_active_chains",
+        "set_timing_mode",
+        "data_port_loopback"
+    ]
+
+    def __init__(self, slot_idx, clock_rate_cb, **kwargs):
+        super().__init__(slot_idx, **kwargs)
+        self.clock_rate_cb = clock_rate_cb
+        self.master_clock_rate = 122.88e6
+
+    def get_master_clock_rate(self):
+        return self.master_clock_rate
+
+    def set_catalina_clock_rate(self, rate):
+        self.clock_rate_cb(rate)
+        return rate