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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-07-07 15:13:11 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-07-07 15:15:17 -0700 |
| commit | a44f791a44fc248f82da070cd6ea2405cf4532f6 (patch) | |
| tree | 07298e730432b16ae56de92d744faeb58bb2a85b | |
| parent | d48030e8b3fe8b4bf99f689d3412d1fccddd698b (diff) | |
| download | uhd-a44f791a44fc248f82da070cd6ea2405cf4532f6.tar.gz uhd-a44f791a44fc248f82da070cd6ea2405cf4532f6.tar.bz2 uhd-a44f791a44fc248f82da070cd6ea2405cf4532f6.zip | |
x300: Added FPGA->ADC Clock delay for rev 7+ boards
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index d9c3a1177..350e9e9bc 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -52,7 +52,7 @@ static const x300_clk_delays X300_REV0_6_CLK_DELAYS = x300_clk_delays( /*fpga=*/0.900, /*adc=*/0.000, /*dac=*/0.900, /*db_rx=*/0.000, /*db_tx=*/0.000); static const x300_clk_delays X300_REV7_CLK_DELAYS = x300_clk_delays( - /*fpga=*/0.900, /*adc=*/0.000, /*dac=*/0.900, /*db_rx=*/0.000, /*db_tx=*/0.000); + /*fpga=*/0.000, /*adc=*/4.400, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); using namespace uhd; |