fpga: usrp2: update build tools to use python3

2 files changed, 6 insertions, 6 deletions

diff --git a/fpga/usrp2/top/extract_usage.py b/fpga/usrp2/top/extract_usage.py
index 6e6fac206..ebd5827b6 100755
--- a/fpga/usrp2/top/extract_usage.py
+++ b/fpga/usrp2/top/extract_usage.py
@@ -40,7 +40,7 @@ def extract_maps():
     for line in ALL_MAP_FILES.splitlines():
         path, name = line.split()
         if not os.path.exists(path):
-            print 'DNE ', path, ' skipping...'
+            print('DNE {} skipping...'.format(path))
         output += """
 
 
@@ -54,5 +54,5 @@ def extract_maps():
 
 if __name__ == '__main__':
     summary = extract_maps()
-    if len(sys.argv) == 1: print summary
+    if len(sys.argv) == 1: print(summary)
     else: open(sys.argv[1], 'w').write(summary)
diff --git a/fpga/usrp2/top/python/check_inout.py b/fpga/usrp2/top/python/check_inout.py
index ff371d378..49330344b 100755
--- a/fpga/usrp2/top/python/check_inout.py
+++ b/fpga/usrp2/top/python/check_inout.py
@@ -23,8 +23,8 @@ import sys
 import re
 
 if __name__=='__main__':
-  if len(sys.argv) == 2:
-    print "Usage: %s <top level Verilog file> <pin definition UCF>"
+  if len(sys.argv) != 3:
+    print("Usage: {} <top level Verilog file> <pin definition UCF>".format(sys.argv[0]))
     sys.exit(-1)
 
   verilog_filename = sys.argv[1]
@@ -52,11 +52,11 @@ if __name__=='__main__':
 
   for item in verilog_iolist:
     if item not in ucf_iolist:
-      print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item
+      print("Error: {} appears in the top-level Verilog file, but is not in the UCF definition file!".format(item))
       err = True
 
   if err:
     sys.exit(-1)
 
-  print "No errors found."
+  print("No errors found.")
   sys.exit(0)