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| author | Steve Czabaniuk <steve.czabaniuk@ni.com> | 2020-07-01 11:11:08 -0500 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2020-07-09 00:41:50 -0700 |
| commit | 74c381f5e4c28bc794720ed2a46e2ec62d0fa2f7 (patch) | |
| tree | 6d525e551987d747ad2e4a3bffaed240f0fe97d6 | |
| parent | 5f79b8e3789247b74ce99a1a20c0158d77581688 (diff) | |
| download | uhd-74c381f5e4c28bc794720ed2a46e2ec62d0fa2f7.tar.gz uhd-74c381f5e4c28bc794720ed2a46e2ec62d0fa2f7.tar.bz2 uhd-74c381f5e4c28bc794720ed2a46e2ec62d0fa2f7.zip | |
docs: n3xx: Include WX in table of N320 images
| -rw-r--r-- | host/docs/usrp_n3xx.dox | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/host/docs/usrp_n3xx.dox b/host/docs/usrp_n3xx.dox index fe0570389..0e8e90830 100644 --- a/host/docs/usrp_n3xx.dox +++ b/host/docs/usrp_n3xx.dox @@ -1471,14 +1471,14 @@ channel configuration with a single shared LO source. The protocols supported on the SFP+ and QSFP+ ports depend on the FPGA image currently loaded. -Interface | HG | XG | XQ | AQ --------------|--------|--------|--------------|-------- -SFP+ 0 | 1 GbE | 10 GbE | White Rabbit | 10 GbE -SFP+ 1 | 10 GbE | 10 GbE | Unused | 10 GbE -QSFP+ lane 0 | Unused | Unused | 10 GbE | Aurora -QSFP+ lane 1 | Unused | Unused | 10 GbE | Aurora -QSFP+ lane 2 | Unused | Unused | Unused | Aurora -QSFP+ lane 3 | Unused | Unused | Unused | Aurora +Interface | HG | XG | WX | XQ | AQ +-------------|--------|--------|--------------|--------------|-------- +SFP+ 0 | 1 GbE | 10 GbE | White Rabbit | White Rabbit | 10 GbE +SFP+ 1 | 10 GbE | 10 GbE | 10 GbE | Unused | 10 GbE +QSFP+ lane 0 | Unused | Unused | Unused | 10 GbE | Aurora +QSFP+ lane 1 | Unused | Unused | Unused | 10 GbE | Aurora +QSFP+ lane 2 | Unused | Unused | Unused | Unused | Aurora +QSFP+ lane 3 | Unused | Unused | Unused | Unused | Aurora \subsection n3xx_rh_eeprom_flags EEPROM flags |