fpga: Use PROTOVER and CHDR_W from RFNoC image builder

This updates all RFNoC devices so that they get the RFNoC protocol
version and CHDR width in the same way, from the output generated by
the RFNoC image builder.

13 files changed, 113 insertions, 27 deletions

diff --git a/fpga/usrp3/top/e31x/Makefile.e31x.inc b/fpga/usrp3/top/e31x/Makefile.e31x.inc
index 4e017ca0c..871dd5318 100644
--- a/fpga/usrp3/top/e31x/Makefile.e31x.inc
+++ b/fpga/usrp3/top/e31x/Makefile.e31x.inc
@@ -107,13 +107,14 @@ $(RFNOC_BLOCK_EXAMPLE_SRCS) \
 $(abspath $(MB_XDC))
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
+IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
 
 ##################################################
 # Dependency Targets
 ##################################################
 .SECONDEXPANSION:
 
-VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
+VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
 
 # DESIGN_SRCS and VERILOG_DEFS must be defined
 bin: .prereqs $$(DESIGN_SRCS) ip
diff --git a/fpga/usrp3/top/e31x/e31x.v b/fpga/usrp3/top/e31x/e31x.v
index 57c1346ff..9ca3db62e 100644
--- a/fpga/usrp3/top/e31x/e31x.v
+++ b/fpga/usrp3/top/e31x/e31x.v
@@ -136,6 +136,22 @@ module e31x (
   inout [5:0]   PL_GPIO
 );
 
+  // Include the RFNoC image core header file
+  `ifdef RFNOC_IMAGE_CORE_HDR
+    `include `"`RFNOC_IMAGE_CORE_HDR`"
+  `else
+    ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+    `define CHDR_WIDTH     64
+    `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+  `endif
+  localparam CHDR_W         = `CHDR_WIDTH;
+  localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
+
+  // This USRP currently only supports 64-bit CHDR width
+  if (CHDR_W != 64) begin : gen_chdr_w_error
+    CHDR_W_must_be_64_for_this_USRP();
+  end
+
   // Constants
   localparam REG_AWIDTH = 14; // log2(0x4000)
   localparam REG_DWIDTH = 32;
@@ -846,7 +862,9 @@ module e31x (
     .NUM_DBOARDS(NUM_DBOARDS),
     .NUM_CHANNELS_PER_DBOARD(NUM_CHANNELS_PER_RADIO),
     .FP_GPIO_WIDTH(FP_GPIO_WIDTH),
-    .DB_GPIO_WIDTH(DB_GPIO_WIDTH)
+    .DB_GPIO_WIDTH(DB_GPIO_WIDTH),
+    .CHDR_W(CHDR_W),
+    .RFNOC_PROTOVER(RFNOC_PROTOVER)
   ) e31x_core_inst (
 
     //Clocks and resets
diff --git a/fpga/usrp3/top/e31x/e31x_core.v b/fpga/usrp3/top/e31x/e31x_core.v
index 99675262b..43bb59799 100644
--- a/fpga/usrp3/top/e31x/e31x_core.v
+++ b/fpga/usrp3/top/e31x/e31x_core.v
@@ -26,7 +26,7 @@ module e31x_core #(
   parameter NUM_CHANNELS_PER_DBOARD = 2,
   parameter FP_GPIO_WIDTH = 8,  // Front panel GPIO width
   parameter DB_GPIO_WIDTH = 16,  // Daughterboard GPIO width
-  parameter CHDR_WIDTH  = 16'd64 ,
+  parameter CHDR_W = 64,
   parameter RFNOC_PROTOVER  = {8'd1, 8'd0}
 )(
   // Clocks and resets
@@ -414,7 +414,7 @@ module e31x_core #(
             cp_glob_resp_data <= {16'd0, device_id};
 
           REG_RFNOC_INFO:
-            cp_glob_resp_data <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]};
+            cp_glob_resp_data <= {CHDR_W[15:0], RFNOC_PROTOVER[15:0]};
 
           REG_COMPAT_NUM:
             cp_glob_resp_data <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]};
@@ -812,7 +812,8 @@ module e31x_core #(
   /////////////////////////////////////////////////////////////////////////////
 
   rfnoc_image_core #(
-    .PROTOVER(RFNOC_PROTOVER)
+    .CHDR_W   (CHDR_W),
+    .PROTOVER (RFNOC_PROTOVER)
   ) rfnoc_image_core_i (
     .chdr_aclk               (bus_clk    ),
     .ctrl_aclk               (clk40      ),
diff --git a/fpga/usrp3/top/e320/Makefile.e320.inc b/fpga/usrp3/top/e320/Makefile.e320.inc
index b8544f3cd..c546b7919 100644
--- a/fpga/usrp3/top/e320/Makefile.e320.inc
+++ b/fpga/usrp3/top/e320/Makefile.e320.inc
@@ -120,13 +120,14 @@ $(RFNOC_BLOCK_RADIO_SRCS) \
 $(abspath $(MB_XDC))
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
+IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
 
 ##################################################
 # Dependency Targets
 ##################################################
 .SECONDEXPANSION:
 
-VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
+VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
 
 # DESIGN_SRCS and VERILOG_DEFS must be defined
 bin: .prereqs $$(DESIGN_SRCS) ip
diff --git a/fpga/usrp3/top/e320/e320.v b/fpga/usrp3/top/e320/e320.v
index 501f6a06d..f16d1877f 100644
--- a/fpga/usrp3/top/e320/e320.v
+++ b/fpga/usrp3/top/e320/e320.v
@@ -175,6 +175,22 @@ module e320 (
 
 );
 
+  // Include the RFNoC image core header file
+  `ifdef RFNOC_IMAGE_CORE_HDR
+    `include `"`RFNOC_IMAGE_CORE_HDR`"
+  `else
+    ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+    `define CHDR_WIDTH     64
+    `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+  `endif
+  localparam CHDR_W         = `CHDR_WIDTH;
+  localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
+
+  // This USRP currently only supports 64-bit CHDR width
+  if (CHDR_W != 64) begin : gen_chdr_w_error
+    CHDR_W_must_be_64_for_this_USRP();
+  end
+
   `ifdef SFP_1GBE
     parameter PROTOCOL = "1GbE";
     parameter MDIO_EN = 1'b1;
@@ -207,7 +223,6 @@ module e320 (
   localparam NUM_CHANNELS_PER_RADIO = 2;
   localparam NUM_DBOARDS = 1;
   localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO;
-  localparam [15:0] RFNOC_PROTOVER  = {8'd1, 8'd0};
 
   // Clocks
   wire xgige_clk156;
@@ -1690,7 +1705,9 @@ module e320 (
     .NUM_CHANNELS(NUM_CHANNELS),
     .NUM_DBOARDS(NUM_DBOARDS),
     .FP_GPIO_WIDTH(FP_GPIO_WIDTH),
-    .DB_GPIO_WIDTH(DB_GPIO_WIDTH)
+    .DB_GPIO_WIDTH(DB_GPIO_WIDTH),
+    .CHDR_W(CHDR_W),
+    .RFNOC_PROTOVER(RFNOC_PROTOVER)
   ) e320_core_i (
 
     //Clocks and resets
diff --git a/fpga/usrp3/top/e320/e320_core.v b/fpga/usrp3/top/e320/e320_core.v
index a63bdda91..a49f28bf1 100644
--- a/fpga/usrp3/top/e320/e320_core.v
+++ b/fpga/usrp3/top/e320/e320_core.v
@@ -25,7 +25,7 @@ module e320_core #(
   parameter NUM_CHANNELS_PER_DBOARD = 2,
   parameter FP_GPIO_WIDTH = 8,  // Front panel GPIO width
   parameter DB_GPIO_WIDTH = 16,  // Daughterboard GPIO width
-  parameter CHDR_WIDTH  = 16'd64 ,
+  parameter CHDR_W = 64,
   parameter RFNOC_PROTOVER  = {8'd1, 8'd0}
 )(
   // Clocks and resets
@@ -468,7 +468,7 @@ module e320_core #(
             cp_glob_resp_data <= { 16'd0, device_id };
 
           REG_RFNOC_INFO:
-            cp_glob_resp_data <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]};
+            cp_glob_resp_data <= {CHDR_W[15:0], RFNOC_PROTOVER[15:0]};
 
           REG_COMPAT_NUM:
             cp_glob_resp_data <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]};
@@ -1028,7 +1028,8 @@ module e320_core #(
   end
 
   rfnoc_image_core #(
-    .PROTOVER(RFNOC_PROTOVER)
+    .CHDR_W   (CHDR_W),
+    .PROTOVER (RFNOC_PROTOVER)
   ) rfnoc_sandbox_i (
     .chdr_aclk               (bus_clk    ),
     .ctrl_aclk               (clk40      ),
diff --git a/fpga/usrp3/top/n3xx/Makefile b/fpga/usrp3/top/n3xx/Makefile
index f1aef0c68..8bbe2dd42 100644
--- a/fpga/usrp3/top/n3xx/Makefile
+++ b/fpga/usrp3/top/n3xx/Makefile
@@ -34,12 +34,12 @@ XQ_DEFS=SFP0_WR=1     QSFP_10GBE=1  USE_REPLAY=1   BUILD_WR=1     BUILD_10G=1
 AQ_DEFS=SFP0_10GBE=1  SFP1_10GBE=1  QSFP_AURORA=1  USE_REPLAY=1   BUILD_10G=1    BUILD_AURORA=1    QSFP_LANES=4 $(OPTIONS)
 
 # Defaults specific to the various targets:
-N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n300_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex)
-N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n310_static_router.hex)
-N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n320_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n320_static_router.hex)
-N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n300_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n300_bist_static_router.hex)
-N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n310_bist_static_router.hex)
-N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n320_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n320_bist_static_router.hex)
+N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex)
+N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n310_static_router.hex)
+N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n320_static_router.hex)
+N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_bist_static_router.hex)
+N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n310_bist_static_router.hex)
+N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n320_bist_static_router.hex)
 
 # Set build option (check RTL, run synthesis, or do a full build)
 ifndef TARGET
diff --git a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc
index 23258b209..b37f84882 100644
--- a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc
+++ b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc
@@ -142,13 +142,14 @@ $(RFNOC_BLOCK_RADIO_SRCS) \
 $(RFNOC_BLOCK_REPLAY_SRCS)
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
+IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
 
 ##################################################
 # Dependency Targets
 ##################################################
 .SECONDEXPANSION:
 
-VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
+VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
 
 # DESIGN_SRCS and VERILOG_DEFS must be defined
 bin: .prereqs $$(DESIGN_SRCS) ip
diff --git a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v
index d9104f412..daa3ca90e 100644
--- a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v
+++ b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v
@@ -315,6 +315,22 @@ module n3xx (
 `endif
 );
 
+  // Include the RFNoC image core header file
+  `ifdef RFNOC_IMAGE_CORE_HDR
+    `include `"`RFNOC_IMAGE_CORE_HDR`"
+  `else
+    ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+    `define CHDR_WIDTH     64
+    `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+  `endif
+  localparam CHDR_W         = `CHDR_WIDTH;
+  localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
+
+  // This USRP currently only supports 64-bit CHDR width
+  if (CHDR_W != 64) begin : gen_chdr_w_error
+    CHDR_W_must_be_64_for_this_USRP();
+  end
+
   localparam N_AXILITE_SLAVES = 4;
   localparam REG_AWIDTH = 14; // log2(0x4000)
   localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -332,7 +348,6 @@ module n3xx (
   localparam NUM_DBOARDS = 1;
 `endif
   localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO;
-  localparam [15:0] RFNOC_PROTOVER  = {8'd1, 8'd0};
 
   // Internal connections to PS
   // HP0 -- High Performance port 0, FPGA is the master
@@ -3517,6 +3532,8 @@ module n3xx (
     .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO),
     .NUM_CHANNELS(NUM_CHANNELS),
     .NUM_DBOARDS(NUM_DBOARDS),
+    .CHDR_W(CHDR_W),
+    .RFNOC_PROTOVER(RFNOC_PROTOVER),
   `ifdef USE_REPLAY
     .USE_REPLAY(1)
   `else
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v
index 9eedd55b9..e5238f135 100644
--- a/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v
+++ b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v
@@ -307,6 +307,22 @@ module n3xx (
   output        DBB_LED_TX
 );
 
+  // Include the RFNoC image core header file
+  `ifdef RFNOC_IMAGE_CORE_HDR
+    `include `"`RFNOC_IMAGE_CORE_HDR`"
+  `else
+    ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+    `define CHDR_WIDTH     64
+    `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+  `endif
+  localparam CHDR_W         = `CHDR_WIDTH;
+  localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
+
+  // This USRP currently only supports 64-bit CHDR width
+  if (CHDR_W != 64) begin : gen_chdr_w_error
+    CHDR_W_must_be_64_for_this_USRP();
+  end
+
   localparam N_AXILITE_SLAVES = 4;
   localparam REG_AWIDTH = 14; // log2(0x4000)
   localparam QSFP_REG_AWIDTH = 17; // log2(0x20000)
@@ -320,7 +336,6 @@ module n3xx (
   localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO;
   localparam CHANNEL_WIDTH = 32;
 
-
   // Internal connections to PS
   // HP0 -- High Performance port 0, FPGA is the master
   wire [31:0] S_AXI_HP0_AWADDR;
@@ -3447,6 +3462,8 @@ module n3xx (
     .NUM_DBOARDS(NUM_DBOARDS),
     .NUM_SPI_PER_DBOARD(4),
     .USE_CORRECTION(1),
+    .CHDR_W(CHDR_W),
+    .RFNOC_PROTOVER(RFNOC_PROTOVER),
   `ifdef USE_REPLAY
     .USE_REPLAY(1)
   `else
diff --git a/fpga/usrp3/top/n3xx/n3xx_core.v b/fpga/usrp3/top/n3xx/n3xx_core.v
index 406285824..af43966ad 100644
--- a/fpga/usrp3/top/n3xx/n3xx_core.v
+++ b/fpga/usrp3/top/n3xx/n3xx_core.v
@@ -26,8 +26,8 @@ module n3xx_core #(
   parameter USE_CORRECTION = 0,
   parameter USE_REPLAY = 0,     // 1 for Replay block instead of DMA FIFO
   parameter FP_GPIO_WIDTH = 12, // Front panel GPIO width
-  parameter RFNOC_PROTOVER  = {8'd1, 8'd0},
-  parameter CHDR_WIDTH  = 16'd64
+  parameter CHDR_W = 64,
+  parameter RFNOC_PROTOVER = {8'd1, 8'd0}
 )(
   // Clocks and resets
   input         radio_clk,
@@ -535,7 +535,7 @@ module n3xx_core #(
             cp_glob_resp_data <= {16'd0, device_id};
 
           REG_RFNOC_INFO:
-            cp_glob_resp_data <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]};
+            cp_glob_resp_data <= {CHDR_W[15:0], RFNOC_PROTOVER[15:0]};
 
           REG_COMPAT_NUM:
             cp_glob_resp_data <= {COMPAT_MAJOR, COMPAT_MINOR};
@@ -1118,7 +1118,8 @@ module n3xx_core #(
 
 
   rfnoc_image_core #(
-    .PROTOVER(RFNOC_PROTOVER)
+    .CHDR_W   (CHDR_W),
+    .PROTOVER (RFNOC_PROTOVER)
   ) rfnoc_sandbox_i (
     .chdr_aclk               (bus_clk    ),
     .ctrl_aclk               (clk40      ),
diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc
index 1f18cbf02..1664869b2 100644
--- a/fpga/usrp3/top/x300/Makefile.x300.inc
+++ b/fpga/usrp3/top/x300/Makefile.x300.inc
@@ -114,13 +114,14 @@ $(RFNOC_BLOCK_REPLAY_SRCS) \
 $(RFNOC_OOT_SRCS)
 
 EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
+IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)"
 
 ##################################################
 # Dependency Targets
 ##################################################
 .SECONDEXPANSION:
 
-VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF)
+VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
 
 # DESIGN_SRCS and VERILOG_DEFS must be defined
 bin: .prereqs $$(DESIGN_SRCS) ip
diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v
index 90f840a4c..e97ff7ef8 100644
--- a/fpga/usrp3/top/x300/bus_int.v
+++ b/fpga/usrp3/top/x300/bus_int.v
@@ -177,7 +177,16 @@ module bus_int #(
    localparam COMPAT_MINOR       = 16'h0000;
    localparam NUM_TIMEKEEPERS    = 1;
 
-   localparam [15:0] RFNOC_PROTOVER  = {8'd1, 8'd0};
+   // Include the RFNoC image core header file
+   `ifdef RFNOC_IMAGE_CORE_HDR
+     `include `"`RFNOC_IMAGE_CORE_HDR`"
+   `else
+     ERROR_RFNOC_IMAGE_CORE_HDR_not_defined();
+     `define CHDR_WIDTH     64
+     `define RFNOC_PROTOVER { 8'd1, 8'd0 }
+   `endif
+   localparam CHDR_W         = `CHDR_WIDTH;
+   localparam RFNOC_PROTOVER = `RFNOC_PROTOVER;
 
    wire [31:0] 	        set_data;
    wire [7:0] 	        set_addr;
@@ -733,7 +742,8 @@ module bus_int #(
     ///////////////////////////////////////////////////////////////////////////
 
   rfnoc_image_core #(
-    .PROTOVER(RFNOC_PROTOVER)
+    .CHDR_W   (CHDR_W),
+    .PROTOVER (RFNOC_PROTOVER)
   ) rfnoc_sandbox_i (
     .chdr_aclk               (clk        ),
     .ctrl_aclk               (clk_div2   ),