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authorAaron Rossetto <aaron.rossetto@ni.com>2022-06-03 15:21:25 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2022-06-10 13:24:05 -0500
commit6a8653d2c9a64b77335d0d941632f191815fab4e (patch)
treec35e6ee50aebba9047808948fdbd84199f6004e4
parent79f12bb44a1246191e3ea4a8760c474c8085669d (diff)
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N320: Revert PLL lock time reduction
This commit reverts the changes made in commit 81a9cc1f8 to reduce the time for the LMK PLL to report lock status. The decision to revert the change comes after an investigation found that reducing the overall time to detect lock correlates with an increase in an error reported by the TDC ('[ERROR] TDC measurements show a wide range of values! Check your clock rates for incompatibilities. ... Uncaught exception in method set_clock_source: TDC measurement out of expected range!'). Despite the LMK PLL reporting lock status, our investigation revealed that it takes additional time for the PLL to align the daughterboards' clocks closely enough to pass the TDC measurement's range limit (i.e., no samples exceeding the measurement mean +/- 500 ps). Reverting the change increases the amount of time between achieving lock status and taking the TDC measurements, thus greatly reducing the likelihood of the reported error.
-rw-r--r--mpm/python/usrp_mpm/dboard_manager/lmk_rh.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_rh.py b/mpm/python/usrp_mpm/dboard_manager/lmk_rh.py
index d2745b631..c18e6ec92 100644
--- a/mpm/python/usrp_mpm/dboard_manager/lmk_rh.py
+++ b/mpm/python/usrp_mpm/dboard_manager/lmk_rh.py
@@ -216,8 +216,8 @@ class LMK04828Rh(LMK04828):
(0x159, (self.pll1_n_divider & 0x3F00) >> 8), # PLL1 N divider [13:8], default = d6
(0x15A, (self.pll1_n_divider & 0x00FF) >> 0), # PLL1 N divider [7:0], default = d0
(0x15B, 0xC7), # PLL1 PFD: negative slope for active filter / CP = 750 uA
- (0x15C, 0x0F), # PLL1 DLD Count [13:8]
- (0x15D, 0xA0), # PLL1 DLD Count [7:0]
+ (0x15C, 0x27), # PLL1 DLD Count [13:8]
+ (0x15D, 0x10), # PLL1 DLD Count [7:0]
(0x15E, 0x00), # PLL1 R/N delay, defaults = 0
(0x15F, 0x0B), # Status LD1 pin = PLL1 LD, push-pull output
(0x160, (self.pll2_r_divider & 0x0F00) >> 8), # PLL2 R divider [11:8];