fpga: x400: Update rfnoc_image_core files

Updates the RFNoC image core files to include DRAM and default image
changes.

8 files changed, 1327 insertions, 98 deletions

diff --git a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v
index f9a619749..398ef32dd 100644
--- a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -13,9 +13,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:46:03.650065
-// Source: x410_100_rfnoc_image_core.yml
-// Source SHA256: cb326c48a67d58ce1151b83a8943f02c24509946f974f9b1b090bc1780915f8a
+// File generated on: 2022-02-02T14:39:07.260299
+// Source: ./x410_100_rfnoc_image_core.yml
+// Source SHA256: 0171fb376a68431d88c4d9a1f5b69c5b20ebb0e5b4efacb34173f9349a25e3d9
 //
 
 `default_nettype none
@@ -33,6 +33,7 @@ module rfnoc_image_core #(
   input  wire         core_arst,
   input  wire         radio_clk,
   input  wire         radio_2x_clk,
+  input  wire         dram_clk,
   // Basic
   input  wire [  15:0] device_id,
 
@@ -76,6 +77,52 @@ module rfnoc_image_core #(
   output wire [ 255:0] radio_tx_data_radio1,
   input  wire [   7:0] radio_tx_stb_radio1,
   output wire [   7:0] radio_tx_running_radio1,
+  // dram
+  input  wire [   0:0] axi_rst,
+  output wire [   3:0] m_axi_awid,
+  output wire [ 191:0] m_axi_awaddr,
+  output wire [  31:0] m_axi_awlen,
+  output wire [  11:0] m_axi_awsize,
+  output wire [   7:0] m_axi_awburst,
+  output wire [   3:0] m_axi_awlock,
+  output wire [  15:0] m_axi_awcache,
+  output wire [  11:0] m_axi_awprot,
+  output wire [  15:0] m_axi_awqos,
+  output wire [  15:0] m_axi_awregion,
+  output wire [   3:0] m_axi_awuser,
+  output wire [   3:0] m_axi_awvalid,
+  input  wire [   3:0] m_axi_awready,
+  output wire [2047:0] m_axi_wdata,
+  output wire [ 255:0] m_axi_wstrb,
+  output wire [   3:0] m_axi_wlast,
+  output wire [   3:0] m_axi_wuser,
+  output wire [   3:0] m_axi_wvalid,
+  input  wire [   3:0] m_axi_wready,
+  input  wire [   3:0] m_axi_bid,
+  input  wire [   7:0] m_axi_bresp,
+  input  wire [   3:0] m_axi_buser,
+  input  wire [   3:0] m_axi_bvalid,
+  output wire [   3:0] m_axi_bready,
+  output wire [   3:0] m_axi_arid,
+  output wire [ 191:0] m_axi_araddr,
+  output wire [  31:0] m_axi_arlen,
+  output wire [  11:0] m_axi_arsize,
+  output wire [   7:0] m_axi_arburst,
+  output wire [   3:0] m_axi_arlock,
+  output wire [  15:0] m_axi_arcache,
+  output wire [  11:0] m_axi_arprot,
+  output wire [  15:0] m_axi_arqos,
+  output wire [  15:0] m_axi_arregion,
+  output wire [   3:0] m_axi_aruser,
+  output wire [   3:0] m_axi_arvalid,
+  input  wire [   3:0] m_axi_arready,
+  input  wire [   3:0] m_axi_rid,
+  input  wire [2047:0] m_axi_rdata,
+  input  wire [   7:0] m_axi_rresp,
+  input  wire [   3:0] m_axi_rlast,
+  input  wire [   3:0] m_axi_ruser,
+  input  wire [   3:0] m_axi_rvalid,
+  output wire [   3:0] m_axi_rready,
 
   // Transport Adapters ///////////////
 
@@ -177,10 +224,42 @@ module rfnoc_image_core #(
   wire              ep3_to_xb_tlast ;
   wire              ep3_to_xb_tvalid;
   wire              ep3_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep4_tdata ;
+  wire              xb_to_ep4_tlast ;
+  wire              xb_to_ep4_tvalid;
+  wire              xb_to_ep4_tready;
+  wire [CHDR_W-1:0] ep4_to_xb_tdata ;
+  wire              ep4_to_xb_tlast ;
+  wire              ep4_to_xb_tvalid;
+  wire              ep4_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep5_tdata ;
+  wire              xb_to_ep5_tlast ;
+  wire              xb_to_ep5_tvalid;
+  wire              xb_to_ep5_tready;
+  wire [CHDR_W-1:0] ep5_to_xb_tdata ;
+  wire              ep5_to_xb_tlast ;
+  wire              ep5_to_xb_tvalid;
+  wire              ep5_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep6_tdata ;
+  wire              xb_to_ep6_tlast ;
+  wire              xb_to_ep6_tvalid;
+  wire              xb_to_ep6_tready;
+  wire [CHDR_W-1:0] ep6_to_xb_tdata ;
+  wire              ep6_to_xb_tlast ;
+  wire              ep6_to_xb_tvalid;
+  wire              ep6_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep7_tdata ;
+  wire              xb_to_ep7_tlast ;
+  wire              xb_to_ep7_tvalid;
+  wire              xb_to_ep7_tready;
+  wire [CHDR_W-1:0] ep7_to_xb_tdata ;
+  wire              ep7_to_xb_tlast ;
+  wire              ep7_to_xb_tvalid;
+  wire              ep7_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (10),
+    .NPORTS         (14),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -193,14 +272,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }),
-    .s_axis_tlast   ({ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }),
-    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }),
-    .m_axis_tlast   ({xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }),
-    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep7_to_xb_tdata , ep6_to_xb_tdata , ep5_to_xb_tdata , ep4_to_xb_tdata , ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }),
+    .s_axis_tlast   ({ep7_to_xb_tlast , ep6_to_xb_tlast , ep5_to_xb_tlast , ep4_to_xb_tlast , ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }),
+    .s_axis_tvalid  ({ep7_to_xb_tvalid, ep6_to_xb_tvalid, ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep7_to_xb_tready, ep6_to_xb_tready, ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep7_tdata , xb_to_ep6_tdata , xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }),
+    .m_axis_tlast   ({xb_to_ep7_tlast , xb_to_ep6_tlast , xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }),
+    .m_axis_tvalid  ({xb_to_ep7_tvalid, xb_to_ep6_tvalid, xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep7_tready, xb_to_ep6_tready, xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -488,6 +567,282 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0)
   );
 
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP4 = (4096)/(CHDR_W/8);
+  localparam INGRESS_BUFF_SIZE_EP4 =
+    REQ_BUFF_SIZE_EP4 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP4);
+
+  wire [CHDR_W-1:0] m_ep4_out0_tdata;
+  wire              m_ep4_out0_tlast;
+  wire              m_ep4_out0_tvalid;
+  wire              m_ep4_out0_tready;
+  wire [CHDR_W-1:0] s_ep4_in0_tdata;
+  wire              s_ep4_in0_tlast;
+  wire              s_ep4_in0_tvalid;
+  wire              s_ep4_in0_tready;
+  wire [      31:0] m_ep4_ctrl_tdata,  s_ep4_ctrl_tdata;
+  wire              m_ep4_ctrl_tlast,  s_ep4_ctrl_tlast;
+  wire              m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
+  wire              m_ep4_ctrl_tready, s_ep4_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (4),
+    .CTRL_XBAR_PORT     (5),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP4),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep4_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep4_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep4_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep4_tvalid),
+    .s_axis_chdr_tready (xb_to_ep4_tready),
+    .m_axis_chdr_tdata  (ep4_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep4_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep4_to_xb_tvalid),
+    .m_axis_chdr_tready (ep4_to_xb_tready),
+    .s_axis_data_tdata  ({s_ep4_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep4_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep4_in0_tvalid}),
+    .s_axis_data_tready ({s_ep4_in0_tready}),
+    .m_axis_data_tdata  ({m_ep4_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep4_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep4_out0_tvalid}),
+    .m_axis_data_tready ({m_ep4_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep4_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep4_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep4_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep4_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep4_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep4_ctrl_tready),
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
+  );
+
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP5 = (4096)/(CHDR_W/8);
+  localparam INGRESS_BUFF_SIZE_EP5 =
+    REQ_BUFF_SIZE_EP5 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP5);
+
+  wire [CHDR_W-1:0] m_ep5_out0_tdata;
+  wire              m_ep5_out0_tlast;
+  wire              m_ep5_out0_tvalid;
+  wire              m_ep5_out0_tready;
+  wire [CHDR_W-1:0] s_ep5_in0_tdata;
+  wire              s_ep5_in0_tlast;
+  wire              s_ep5_in0_tvalid;
+  wire              s_ep5_in0_tready;
+  wire [      31:0] m_ep5_ctrl_tdata,  s_ep5_ctrl_tdata;
+  wire              m_ep5_ctrl_tlast,  s_ep5_ctrl_tlast;
+  wire              m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
+  wire              m_ep5_ctrl_tready, s_ep5_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (5),
+    .CTRL_XBAR_PORT     (6),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP5),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep5_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep5_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep5_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep5_tvalid),
+    .s_axis_chdr_tready (xb_to_ep5_tready),
+    .m_axis_chdr_tdata  (ep5_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep5_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep5_to_xb_tvalid),
+    .m_axis_chdr_tready (ep5_to_xb_tready),
+    .s_axis_data_tdata  ({s_ep5_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep5_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep5_in0_tvalid}),
+    .s_axis_data_tready ({s_ep5_in0_tready}),
+    .m_axis_data_tdata  ({m_ep5_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep5_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep5_out0_tvalid}),
+    .m_axis_data_tready ({m_ep5_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep5_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep5_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep5_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep5_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep5_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep5_ctrl_tready),
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
+  );
+
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP6 = (4096)/(CHDR_W/8);
+  localparam INGRESS_BUFF_SIZE_EP6 =
+    REQ_BUFF_SIZE_EP6 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP6);
+
+  wire [CHDR_W-1:0] m_ep6_out0_tdata;
+  wire              m_ep6_out0_tlast;
+  wire              m_ep6_out0_tvalid;
+  wire              m_ep6_out0_tready;
+  wire [CHDR_W-1:0] s_ep6_in0_tdata;
+  wire              s_ep6_in0_tlast;
+  wire              s_ep6_in0_tvalid;
+  wire              s_ep6_in0_tready;
+  wire [      31:0] m_ep6_ctrl_tdata,  s_ep6_ctrl_tdata;
+  wire              m_ep6_ctrl_tlast,  s_ep6_ctrl_tlast;
+  wire              m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid;
+  wire              m_ep6_ctrl_tready, s_ep6_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (6),
+    .CTRL_XBAR_PORT     (7),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP6),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep6_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep6_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep6_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep6_tvalid),
+    .s_axis_chdr_tready (xb_to_ep6_tready),
+    .m_axis_chdr_tdata  (ep6_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep6_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep6_to_xb_tvalid),
+    .m_axis_chdr_tready (ep6_to_xb_tready),
+    .s_axis_data_tdata  ({s_ep6_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep6_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep6_in0_tvalid}),
+    .s_axis_data_tready ({s_ep6_in0_tready}),
+    .m_axis_data_tdata  ({m_ep6_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep6_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep6_out0_tvalid}),
+    .m_axis_data_tready ({m_ep6_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep6_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep6_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_ep6_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep6_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep6_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep6_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_ep6_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep6_ctrl_tready),
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
+  );
+
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP7 = (4096)/(CHDR_W/8);
+  localparam INGRESS_BUFF_SIZE_EP7 =
+    REQ_BUFF_SIZE_EP7 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP7);
+
+  wire [CHDR_W-1:0] m_ep7_out0_tdata;
+  wire              m_ep7_out0_tlast;
+  wire              m_ep7_out0_tvalid;
+  wire              m_ep7_out0_tready;
+  wire [CHDR_W-1:0] s_ep7_in0_tdata;
+  wire              s_ep7_in0_tlast;
+  wire              s_ep7_in0_tvalid;
+  wire              s_ep7_in0_tready;
+  wire [      31:0] m_ep7_ctrl_tdata,  s_ep7_ctrl_tdata;
+  wire              m_ep7_ctrl_tlast,  s_ep7_ctrl_tlast;
+  wire              m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid;
+  wire              m_ep7_ctrl_tready, s_ep7_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (7),
+    .CTRL_XBAR_PORT     (8),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP7),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep7_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep7_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep7_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep7_tvalid),
+    .s_axis_chdr_tready (xb_to_ep7_tready),
+    .m_axis_chdr_tdata  (ep7_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep7_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep7_to_xb_tvalid),
+    .m_axis_chdr_tready (ep7_to_xb_tready),
+    .s_axis_data_tdata  ({s_ep7_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep7_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep7_in0_tvalid}),
+    .s_axis_data_tready ({s_ep7_in0_tready}),
+    .m_axis_data_tdata  ({m_ep7_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep7_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep7_out0_tvalid}),
+    .m_axis_data_tready ({m_ep7_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep7_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep7_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_ep7_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep7_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep7_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep7_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_ep7_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep7_ctrl_tready),
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
+  );
+
 
   //---------------------------------------------------------------------------
   // Control Crossbar
@@ -521,10 +876,14 @@ module rfnoc_image_core #(
   wire        m_radio1_ctrl_tlast,  s_radio1_ctrl_tlast;
   wire        m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid;
   wire        m_radio1_ctrl_tready, s_radio1_ctrl_tready;
+  wire [31:0] m_replay0_ctrl_tdata,  s_replay0_ctrl_tdata;
+  wire        m_replay0_ctrl_tlast,  s_replay0_ctrl_tlast;
+  wire        m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
+  wire        m_replay0_ctrl_tready, s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (8),
+    .NPORTS           (9),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -533,14 +892,14 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
@@ -549,18 +908,18 @@ module rfnoc_image_core #(
   // RFNoC Core Kernel
   //---------------------------------------------------------------------------
 
-  wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'hA400),
     .DEVICE_FAMILY       ("ULTRASCALE"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (6),
-    .NUM_STREAM_ENDPOINTS(4),
+    .NUM_BLOCKS          (7),
+    .NUM_STREAM_ENDPOINTS(8),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (6),
-    .NUM_EDGES           (16),
+    .NUM_EDGES           (24),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -937,6 +1296,143 @@ module rfnoc_image_core #(
     .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
   );
 
+  //-----------------------------------
+  // replay0
+  //-----------------------------------
+
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  // axi_ram
+  wire [   0:0] replay0_axi_rst;
+  wire [   3:0] replay0_m_axi_awid;
+  wire [ 191:0] replay0_m_axi_awaddr;
+  wire [  31:0] replay0_m_axi_awlen;
+  wire [  11:0] replay0_m_axi_awsize;
+  wire [   7:0] replay0_m_axi_awburst;
+  wire [   3:0] replay0_m_axi_awlock;
+  wire [  15:0] replay0_m_axi_awcache;
+  wire [  11:0] replay0_m_axi_awprot;
+  wire [  15:0] replay0_m_axi_awqos;
+  wire [  15:0] replay0_m_axi_awregion;
+  wire [   3:0] replay0_m_axi_awuser;
+  wire [   3:0] replay0_m_axi_awvalid;
+  wire [   3:0] replay0_m_axi_awready;
+  wire [2047:0] replay0_m_axi_wdata;
+  wire [ 255:0] replay0_m_axi_wstrb;
+  wire [   3:0] replay0_m_axi_wlast;
+  wire [   3:0] replay0_m_axi_wuser;
+  wire [   3:0] replay0_m_axi_wvalid;
+  wire [   3:0] replay0_m_axi_wready;
+  wire [   3:0] replay0_m_axi_bid;
+  wire [   7:0] replay0_m_axi_bresp;
+  wire [   3:0] replay0_m_axi_buser;
+  wire [   3:0] replay0_m_axi_bvalid;
+  wire [   3:0] replay0_m_axi_bready;
+  wire [   3:0] replay0_m_axi_arid;
+  wire [ 191:0] replay0_m_axi_araddr;
+  wire [  31:0] replay0_m_axi_arlen;
+  wire [  11:0] replay0_m_axi_arsize;
+  wire [   7:0] replay0_m_axi_arburst;
+  wire [   3:0] replay0_m_axi_arlock;
+  wire [  15:0] replay0_m_axi_arcache;
+  wire [  11:0] replay0_m_axi_arprot;
+  wire [  15:0] replay0_m_axi_arqos;
+  wire [  15:0] replay0_m_axi_arregion;
+  wire [   3:0] replay0_m_axi_aruser;
+  wire [   3:0] replay0_m_axi_arvalid;
+  wire [   3:0] replay0_m_axi_arready;
+  wire [   3:0] replay0_m_axi_rid;
+  wire [2047:0] replay0_m_axi_rdata;
+  wire [   7:0] replay0_m_axi_rresp;
+  wire [   3:0] replay0_m_axi_rlast;
+  wire [   3:0] replay0_m_axi_ruser;
+  wire [   3:0] replay0_m_axi_rvalid;
+  wire [   3:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID         (8),
+    .CHDR_W              (CHDR_W),
+    .NUM_PORTS           (4),
+    .MEM_DATA_W          (64),
+    .MEM_ADDR_W          (32),
+    .MTU                 (MTU)
+  ) b_replay0_6 (
+    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
+    .mem_clk             (replay0_mem_clk),
+    .rfnoc_core_config   (rfnoc_core_config[512*7-1:512*6]),
+    .rfnoc_core_status   (rfnoc_core_status[512*7-1:512*6]),
+    .axi_rst             (replay0_axi_rst),
+    .m_axi_awid          (replay0_m_axi_awid),
+    .m_axi_awaddr        (replay0_m_axi_awaddr),
+    .m_axi_awlen         (replay0_m_axi_awlen),
+    .m_axi_awsize        (replay0_m_axi_awsize),
+    .m_axi_awburst       (replay0_m_axi_awburst),
+    .m_axi_awlock        (replay0_m_axi_awlock),
+    .m_axi_awcache       (replay0_m_axi_awcache),
+    .m_axi_awprot        (replay0_m_axi_awprot),
+    .m_axi_awqos         (replay0_m_axi_awqos),
+    .m_axi_awregion      (replay0_m_axi_awregion),
+    .m_axi_awuser        (replay0_m_axi_awuser),
+    .m_axi_awvalid       (replay0_m_axi_awvalid),
+    .m_axi_awready       (replay0_m_axi_awready),
+    .m_axi_wdata         (replay0_m_axi_wdata),
+    .m_axi_wstrb         (replay0_m_axi_wstrb),
+    .m_axi_wlast         (replay0_m_axi_wlast),
+    .m_axi_wuser         (replay0_m_axi_wuser),
+    .m_axi_wvalid        (replay0_m_axi_wvalid),
+    .m_axi_wready        (replay0_m_axi_wready),
+    .m_axi_bid           (replay0_m_axi_bid),
+    .m_axi_bresp         (replay0_m_axi_bresp),
+    .m_axi_buser         (replay0_m_axi_buser),
+    .m_axi_bvalid        (replay0_m_axi_bvalid),
+    .m_axi_bready        (replay0_m_axi_bready),
+    .m_axi_arid          (replay0_m_axi_arid),
+    .m_axi_araddr        (replay0_m_axi_araddr),
+    .m_axi_arlen         (replay0_m_axi_arlen),
+    .m_axi_arsize        (replay0_m_axi_arsize),
+    .m_axi_arburst       (replay0_m_axi_arburst),
+    .m_axi_arlock        (replay0_m_axi_arlock),
+    .m_axi_arcache       (replay0_m_axi_arcache),
+    .m_axi_arprot        (replay0_m_axi_arprot),
+    .m_axi_arqos         (replay0_m_axi_arqos),
+    .m_axi_arregion      (replay0_m_axi_arregion),
+    .m_axi_aruser        (replay0_m_axi_aruser),
+    .m_axi_arvalid       (replay0_m_axi_arvalid),
+    .m_axi_arready       (replay0_m_axi_arready),
+    .m_axi_rid           (replay0_m_axi_rid),
+    .m_axi_rdata         (replay0_m_axi_rdata),
+    .m_axi_rresp         (replay0_m_axi_rresp),
+    .m_axi_rlast         (replay0_m_axi_rlast),
+    .m_axi_ruser         (replay0_m_axi_ruser),
+    .m_axi_rvalid        (replay0_m_axi_rvalid),
+    .m_axi_rready        (replay0_m_axi_rready),
+    .s_rfnoc_chdr_tdata  ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast  ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid ({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready ({s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata  ({m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast  ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid ({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready ({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata  (s_replay0_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast  (s_replay0_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready (s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata  (m_replay0_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast  (m_replay0_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
+  );
+
   //---------------------------------------------------------------------------
   // Static Router
   //---------------------------------------------------------------------------
@@ -1021,6 +1517,46 @@ module rfnoc_image_core #(
   assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid;
   assign m_ddc1_out_1_tready = s_ep3_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep4_out0_tdata;
+  assign s_replay0_in_0_tlast = m_ep4_out0_tlast;
+  assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid;
+  assign m_ep4_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep4_in0_tdata = m_replay0_out_0_tdata;
+  assign s_ep4_in0_tlast = m_replay0_out_0_tlast;
+  assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep4_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep5_out0_tdata;
+  assign s_replay0_in_1_tlast = m_ep5_out0_tlast;
+  assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid;
+  assign m_ep5_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep5_in0_tdata = m_replay0_out_1_tdata;
+  assign s_ep5_in0_tlast = m_replay0_out_1_tlast;
+  assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep5_in0_tready;
+
+  assign s_replay0_in_2_tdata = m_ep6_out0_tdata;
+  assign s_replay0_in_2_tlast = m_ep6_out0_tlast;
+  assign s_replay0_in_2_tvalid = m_ep6_out0_tvalid;
+  assign m_ep6_out0_tready = s_replay0_in_2_tready;
+
+  assign s_ep6_in0_tdata = m_replay0_out_2_tdata;
+  assign s_ep6_in0_tlast = m_replay0_out_2_tlast;
+  assign s_ep6_in0_tvalid = m_replay0_out_2_tvalid;
+  assign m_replay0_out_2_tready = s_ep6_in0_tready;
+
+  assign s_replay0_in_3_tdata = m_ep7_out0_tdata;
+  assign s_replay0_in_3_tlast = m_ep7_out0_tlast;
+  assign s_replay0_in_3_tvalid = m_ep7_out0_tvalid;
+  assign m_ep7_out0_tready = s_replay0_in_3_tready;
+
+  assign s_ep7_in0_tdata = m_replay0_out_3_tdata;
+  assign s_ep7_in0_tlast = m_replay0_out_3_tlast;
+  assign s_ep7_in0_tvalid = m_replay0_out_3_tvalid;
+  assign m_replay0_out_3_tready = s_ep7_in0_tready;
+
 
   //---------------------------------------------------------------------------
   // Unused Ports
@@ -1038,6 +1574,7 @@ module rfnoc_image_core #(
   assign radio1_radio_clk = radio_clk;
   assign duc1_ce_clk = radio_clk;
   assign ddc1_ce_clk = radio_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   //---------------------------------------------------------------------------
@@ -1081,6 +1618,52 @@ module rfnoc_image_core #(
   assign radio1_radio_tx_stb = radio_tx_stb_radio1;
   assign radio_tx_running_radio1 = radio1_radio_tx_running;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   // Broadcaster/Listener Connections:
   assign radio0_radio_time = radio_time;
 
diff --git a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh
index a3e3f3a7b..b72dbf932 100644
--- a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -12,9 +12,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:46:03.696404
-// Source: x410_100_rfnoc_image_core.yml
-// Source SHA256: cb326c48a67d58ce1151b83a8943f02c24509946f974f9b1b090bc1780915f8a
+// File generated on: 2022-02-02T14:39:07.293349
+// Source: ./x410_100_rfnoc_image_core.yml
+// Source SHA256: 0171fb376a68431d88c4d9a1f5b69c5b20ebb0e5b4efacb34173f9349a25e3d9
 //
 
 `define CHDR_WIDTH     64
diff --git a/fpga/usrp3/top/x400/x410_100_static_router.hex b/fpga/usrp3/top/x400/x410_100_static_router.hex
index 73449b968..99d1452cd 100644
--- a/fpga/usrp3/top/x400/x410_100_static_router.hex
+++ b/fpga/usrp3/top/x400/x410_100_static_router.hex
@@ -1,17 +1,25 @@
-00000010
-00400140
-014001c0
-01c00180
-01800040
-00800141
-014101c1
-01c10181
-01810080
-00c00200
-02000280
-02800240
-024000c0
-01000201
-02010281
-02810241
-02410100
+00000018
+00400240
+024002c0
+02c00280
+02800040
+00800241
+024102c1
+02c10281
+02810080
+00c00300
+03000380
+03800340
+034000c0
+01000301
+03010381
+03810341
+03410100
+014003c0
+03c00140
+018003c1
+03c10180
+01c003c2
+03c201c0
+020003c3
+03c30200
diff --git a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v
index 9c1bd3c5a..9e71ff039 100644
--- a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -13,9 +13,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:46:07.693716
-// Source: x410_200_rfnoc_image_core.yml
-// Source SHA256: e841d2a58556840a822f9398b8888cc871bf0473c364bcdcb0f46ffce88224c9
+// File generated on: 2022-02-02T14:39:11.377126
+// Source: ./x410_200_rfnoc_image_core.yml
+// Source SHA256: 57ca44ee7facd8ddcd6a88170463ea9665328e011511c8b5d87684fc78b43bd6
 //
 
 `default_nettype none
@@ -33,6 +33,7 @@ module rfnoc_image_core #(
   input  wire         core_arst,
   input  wire         radio_clk,
   input  wire         radio_2x_clk,
+  input  wire         dram_clk,
   // Basic
   input  wire [  15:0] device_id,
 
@@ -76,6 +77,52 @@ module rfnoc_image_core #(
   output wire [ 255:0] radio_tx_data_radio1,
   input  wire [   7:0] radio_tx_stb_radio1,
   output wire [   7:0] radio_tx_running_radio1,
+  // dram
+  input  wire [   0:0] axi_rst,
+  output wire [   3:0] m_axi_awid,
+  output wire [ 191:0] m_axi_awaddr,
+  output wire [  31:0] m_axi_awlen,
+  output wire [  11:0] m_axi_awsize,
+  output wire [   7:0] m_axi_awburst,
+  output wire [   3:0] m_axi_awlock,
+  output wire [  15:0] m_axi_awcache,
+  output wire [  11:0] m_axi_awprot,
+  output wire [  15:0] m_axi_awqos,
+  output wire [  15:0] m_axi_awregion,
+  output wire [   3:0] m_axi_awuser,
+  output wire [   3:0] m_axi_awvalid,
+  input  wire [   3:0] m_axi_awready,
+  output wire [2047:0] m_axi_wdata,
+  output wire [ 255:0] m_axi_wstrb,
+  output wire [   3:0] m_axi_wlast,
+  output wire [   3:0] m_axi_wuser,
+  output wire [   3:0] m_axi_wvalid,
+  input  wire [   3:0] m_axi_wready,
+  input  wire [   3:0] m_axi_bid,
+  input  wire [   7:0] m_axi_bresp,
+  input  wire [   3:0] m_axi_buser,
+  input  wire [   3:0] m_axi_bvalid,
+  output wire [   3:0] m_axi_bready,
+  output wire [   3:0] m_axi_arid,
+  output wire [ 191:0] m_axi_araddr,
+  output wire [  31:0] m_axi_arlen,
+  output wire [  11:0] m_axi_arsize,
+  output wire [   7:0] m_axi_arburst,
+  output wire [   3:0] m_axi_arlock,
+  output wire [  15:0] m_axi_arcache,
+  output wire [  11:0] m_axi_arprot,
+  output wire [  15:0] m_axi_arqos,
+  output wire [  15:0] m_axi_arregion,
+  output wire [   3:0] m_axi_aruser,
+  output wire [   3:0] m_axi_arvalid,
+  input  wire [   3:0] m_axi_arready,
+  input  wire [   3:0] m_axi_rid,
+  input  wire [2047:0] m_axi_rdata,
+  input  wire [   7:0] m_axi_rresp,
+  input  wire [   3:0] m_axi_rlast,
+  input  wire [   3:0] m_axi_ruser,
+  input  wire [   3:0] m_axi_rvalid,
+  output wire [   3:0] m_axi_rready,
 
   // Transport Adapters ///////////////
 
@@ -177,10 +224,42 @@ module rfnoc_image_core #(
   wire              ep3_to_xb_tlast ;
   wire              ep3_to_xb_tvalid;
   wire              ep3_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep4_tdata ;
+  wire              xb_to_ep4_tlast ;
+  wire              xb_to_ep4_tvalid;
+  wire              xb_to_ep4_tready;
+  wire [CHDR_W-1:0] ep4_to_xb_tdata ;
+  wire              ep4_to_xb_tlast ;
+  wire              ep4_to_xb_tvalid;
+  wire              ep4_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep5_tdata ;
+  wire              xb_to_ep5_tlast ;
+  wire              xb_to_ep5_tvalid;
+  wire              xb_to_ep5_tready;
+  wire [CHDR_W-1:0] ep5_to_xb_tdata ;
+  wire              ep5_to_xb_tlast ;
+  wire              ep5_to_xb_tvalid;
+  wire              ep5_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep6_tdata ;
+  wire              xb_to_ep6_tlast ;
+  wire              xb_to_ep6_tvalid;
+  wire              xb_to_ep6_tready;
+  wire [CHDR_W-1:0] ep6_to_xb_tdata ;
+  wire              ep6_to_xb_tlast ;
+  wire              ep6_to_xb_tvalid;
+  wire              ep6_to_xb_tready;
+  wire [CHDR_W-1:0] xb_to_ep7_tdata ;
+  wire              xb_to_ep7_tlast ;
+  wire              xb_to_ep7_tvalid;
+  wire              xb_to_ep7_tready;
+  wire [CHDR_W-1:0] ep7_to_xb_tdata ;
+  wire              ep7_to_xb_tlast ;
+  wire              ep7_to_xb_tvalid;
+  wire              ep7_to_xb_tready;
 
   chdr_crossbar_nxn #(
     .CHDR_W         (CHDR_W),
-    .NPORTS         (10),
+    .NPORTS         (14),
     .DEFAULT_PORT   (0),
     .MTU            (MTU),
     .ROUTE_TBL_SIZE (6),
@@ -193,14 +272,14 @@ module rfnoc_image_core #(
     .clk            (rfnoc_chdr_clk),
     .reset          (rfnoc_chdr_rst),
     .device_id      (device_id),
-    .s_axis_tdata   ({ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }),
-    .s_axis_tlast   ({ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }),
-    .s_axis_tvalid  ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
-    .s_axis_tready  ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}),
-    .m_axis_tdata   ({xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }),
-    .m_axis_tlast   ({xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }),
-    .m_axis_tvalid  ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
-    .m_axis_tready  ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}),
+    .s_axis_tdata   ({ep7_to_xb_tdata , ep6_to_xb_tdata , ep5_to_xb_tdata , ep4_to_xb_tdata , ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }),
+    .s_axis_tlast   ({ep7_to_xb_tlast , ep6_to_xb_tlast , ep5_to_xb_tlast , ep4_to_xb_tlast , ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }),
+    .s_axis_tvalid  ({ep7_to_xb_tvalid, ep6_to_xb_tvalid, ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}),
+    .s_axis_tready  ({ep7_to_xb_tready, ep6_to_xb_tready, ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}),
+    .m_axis_tdata   ({xb_to_ep7_tdata , xb_to_ep6_tdata , xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }),
+    .m_axis_tlast   ({xb_to_ep7_tlast , xb_to_ep6_tlast , xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }),
+    .m_axis_tvalid  ({xb_to_ep7_tvalid, xb_to_ep6_tvalid, xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}),
+    .m_axis_tready  ({xb_to_ep7_tready, xb_to_ep6_tready, xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}),
     .ext_rtcfg_stb  (1'h0),
     .ext_rtcfg_addr (16'h0),
     .ext_rtcfg_data (32'h0),
@@ -488,6 +567,282 @@ module rfnoc_image_core #(
     .signal_data_err    (1'b0)
   );
 
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP4 = (4096)/(CHDR_W/8);
+  localparam INGRESS_BUFF_SIZE_EP4 =
+    REQ_BUFF_SIZE_EP4 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP4);
+
+  wire [CHDR_W-1:0] m_ep4_out0_tdata;
+  wire              m_ep4_out0_tlast;
+  wire              m_ep4_out0_tvalid;
+  wire              m_ep4_out0_tready;
+  wire [CHDR_W-1:0] s_ep4_in0_tdata;
+  wire              s_ep4_in0_tlast;
+  wire              s_ep4_in0_tvalid;
+  wire              s_ep4_in0_tready;
+  wire [      31:0] m_ep4_ctrl_tdata,  s_ep4_ctrl_tdata;
+  wire              m_ep4_ctrl_tlast,  s_ep4_ctrl_tlast;
+  wire              m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid;
+  wire              m_ep4_ctrl_tready, s_ep4_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (4),
+    .CTRL_XBAR_PORT     (5),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP4),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep4_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep4_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep4_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep4_tvalid),
+    .s_axis_chdr_tready (xb_to_ep4_tready),
+    .m_axis_chdr_tdata  (ep4_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep4_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep4_to_xb_tvalid),
+    .m_axis_chdr_tready (ep4_to_xb_tready),
+    .s_axis_data_tdata  ({s_ep4_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep4_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep4_in0_tvalid}),
+    .s_axis_data_tready ({s_ep4_in0_tready}),
+    .m_axis_data_tdata  ({m_ep4_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep4_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep4_out0_tvalid}),
+    .m_axis_data_tready ({m_ep4_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep4_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep4_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep4_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep4_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep4_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep4_ctrl_tready),
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
+  );
+
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP5 = (4096)/(CHDR_W/8);
+  localparam INGRESS_BUFF_SIZE_EP5 =
+    REQ_BUFF_SIZE_EP5 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP5);
+
+  wire [CHDR_W-1:0] m_ep5_out0_tdata;
+  wire              m_ep5_out0_tlast;
+  wire              m_ep5_out0_tvalid;
+  wire              m_ep5_out0_tready;
+  wire [CHDR_W-1:0] s_ep5_in0_tdata;
+  wire              s_ep5_in0_tlast;
+  wire              s_ep5_in0_tvalid;
+  wire              s_ep5_in0_tready;
+  wire [      31:0] m_ep5_ctrl_tdata,  s_ep5_ctrl_tdata;
+  wire              m_ep5_ctrl_tlast,  s_ep5_ctrl_tlast;
+  wire              m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid;
+  wire              m_ep5_ctrl_tready, s_ep5_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (5),
+    .CTRL_XBAR_PORT     (6),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP5),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep5_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep5_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep5_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep5_tvalid),
+    .s_axis_chdr_tready (xb_to_ep5_tready),
+    .m_axis_chdr_tdata  (ep5_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep5_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep5_to_xb_tvalid),
+    .m_axis_chdr_tready (ep5_to_xb_tready),
+    .s_axis_data_tdata  ({s_ep5_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep5_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep5_in0_tvalid}),
+    .s_axis_data_tready ({s_ep5_in0_tready}),
+    .m_axis_data_tdata  ({m_ep5_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep5_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep5_out0_tvalid}),
+    .m_axis_data_tready ({m_ep5_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep5_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep5_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep5_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep5_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep5_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep5_ctrl_tready),
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
+  );
+
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP6 = (4096)/(CHDR_W/8);
+  localparam INGRESS_BUFF_SIZE_EP6 =
+    REQ_BUFF_SIZE_EP6 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP6);
+
+  wire [CHDR_W-1:0] m_ep6_out0_tdata;
+  wire              m_ep6_out0_tlast;
+  wire              m_ep6_out0_tvalid;
+  wire              m_ep6_out0_tready;
+  wire [CHDR_W-1:0] s_ep6_in0_tdata;
+  wire              s_ep6_in0_tlast;
+  wire              s_ep6_in0_tvalid;
+  wire              s_ep6_in0_tready;
+  wire [      31:0] m_ep6_ctrl_tdata,  s_ep6_ctrl_tdata;
+  wire              m_ep6_ctrl_tlast,  s_ep6_ctrl_tlast;
+  wire              m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid;
+  wire              m_ep6_ctrl_tready, s_ep6_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (6),
+    .CTRL_XBAR_PORT     (7),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP6),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep6_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep6_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep6_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep6_tvalid),
+    .s_axis_chdr_tready (xb_to_ep6_tready),
+    .m_axis_chdr_tdata  (ep6_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep6_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep6_to_xb_tvalid),
+    .m_axis_chdr_tready (ep6_to_xb_tready),
+    .s_axis_data_tdata  ({s_ep6_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep6_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep6_in0_tvalid}),
+    .s_axis_data_tready ({s_ep6_in0_tready}),
+    .m_axis_data_tdata  ({m_ep6_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep6_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep6_out0_tvalid}),
+    .m_axis_data_tready ({m_ep6_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep6_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep6_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_ep6_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep6_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep6_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep6_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_ep6_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep6_ctrl_tready),
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
+  );
+
+  // If requested buffer size is 0, use the minimum SRL-based FIFO size.
+  // Otherwise, make sure it's at least two MTU-sized packets.
+  localparam REQ_BUFF_SIZE_EP7 = (4096)/(CHDR_W/8);
+  localparam INGRESS_BUFF_SIZE_EP7 =
+    REQ_BUFF_SIZE_EP7 == 0         ? 5     :
+    REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 :
+    $clog2(REQ_BUFF_SIZE_EP7);
+
+  wire [CHDR_W-1:0] m_ep7_out0_tdata;
+  wire              m_ep7_out0_tlast;
+  wire              m_ep7_out0_tvalid;
+  wire              m_ep7_out0_tready;
+  wire [CHDR_W-1:0] s_ep7_in0_tdata;
+  wire              s_ep7_in0_tlast;
+  wire              s_ep7_in0_tvalid;
+  wire              s_ep7_in0_tready;
+  wire [      31:0] m_ep7_ctrl_tdata,  s_ep7_ctrl_tdata;
+  wire              m_ep7_ctrl_tlast,  s_ep7_ctrl_tlast;
+  wire              m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid;
+  wire              m_ep7_ctrl_tready, s_ep7_ctrl_tready;
+
+  chdr_stream_endpoint #(
+    .PROTOVER           (PROTOVER),
+    .CHDR_W             (CHDR_W),
+    .AXIS_CTRL_EN       (0),
+    .AXIS_DATA_EN       (1),
+    .NUM_DATA_I         (1),
+    .NUM_DATA_O         (1),
+    .INST_NUM           (7),
+    .CTRL_XBAR_PORT     (8),
+    .INGRESS_BUFF_SIZE  (INGRESS_BUFF_SIZE_EP7),
+    .MTU                (MTU),
+    .REPORT_STRM_ERRS   (1)
+  ) ep7_i (
+    .rfnoc_chdr_clk     (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst     (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk     (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst     (rfnoc_ctrl_rst),
+    .device_id          (device_id),
+    .s_axis_chdr_tdata  (xb_to_ep7_tdata),
+    .s_axis_chdr_tlast  (xb_to_ep7_tlast),
+    .s_axis_chdr_tvalid (xb_to_ep7_tvalid),
+    .s_axis_chdr_tready (xb_to_ep7_tready),
+    .m_axis_chdr_tdata  (ep7_to_xb_tdata),
+    .m_axis_chdr_tlast  (ep7_to_xb_tlast),
+    .m_axis_chdr_tvalid (ep7_to_xb_tvalid),
+    .m_axis_chdr_tready (ep7_to_xb_tready),
+    .s_axis_data_tdata  ({s_ep7_in0_tdata}),
+    .s_axis_data_tlast  ({s_ep7_in0_tlast}),
+    .s_axis_data_tvalid ({s_ep7_in0_tvalid}),
+    .s_axis_data_tready ({s_ep7_in0_tready}),
+    .m_axis_data_tdata  ({m_ep7_out0_tdata}),
+    .m_axis_data_tlast  ({m_ep7_out0_tlast}),
+    .m_axis_data_tvalid ({m_ep7_out0_tvalid}),
+    .m_axis_data_tready ({m_ep7_out0_tready}),
+    .s_axis_ctrl_tdata  (s_ep7_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_ep7_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_ep7_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_ep7_ctrl_tready),
+    .m_axis_ctrl_tdata  (m_ep7_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_ep7_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_ep7_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_ep7_ctrl_tready),
+    .strm_seq_err_stb   (),
+    .strm_data_err_stb  (),
+    .strm_route_err_stb (),
+    .signal_data_err    (1'b0)
+  );
+
 
   //---------------------------------------------------------------------------
   // Control Crossbar
@@ -521,10 +876,14 @@ module rfnoc_image_core #(
   wire        m_radio1_ctrl_tlast,  s_radio1_ctrl_tlast;
   wire        m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid;
   wire        m_radio1_ctrl_tready, s_radio1_ctrl_tready;
+  wire [31:0] m_replay0_ctrl_tdata,  s_replay0_ctrl_tdata;
+  wire        m_replay0_ctrl_tlast,  s_replay0_ctrl_tlast;
+  wire        m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid;
+  wire        m_replay0_ctrl_tready, s_replay0_ctrl_tready;
 
   axis_ctrl_crossbar_nxn #(
     .WIDTH            (32),
-    .NPORTS           (8),
+    .NPORTS           (9),
     .TOPOLOGY         ("TORUS"),
     .INGRESS_BUFF_SIZE(5),
     .ROUTER_BUFF_SIZE (5),
@@ -533,14 +892,14 @@ module rfnoc_image_core #(
   ) ctrl_xb_i (
     .clk              (rfnoc_ctrl_clk),
     .reset            (rfnoc_ctrl_rst),
-    .s_axis_tdata     ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
-    .s_axis_tvalid    ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
-    .s_axis_tlast     ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
-    .s_axis_tready    ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
-    .m_axis_tdata     ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
-    .m_axis_tvalid    ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
-    .m_axis_tlast     ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
-    .m_axis_tready    ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
+    .s_axis_tdata     ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }),
+    .s_axis_tvalid    ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}),
+    .s_axis_tlast     ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }),
+    .s_axis_tready    ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}),
+    .m_axis_tdata     ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }),
+    .m_axis_tvalid    ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}),
+    .m_axis_tlast     ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }),
+    .m_axis_tready    ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}),
     .deadlock_detected()
   );
 
@@ -549,18 +908,18 @@ module rfnoc_image_core #(
   // RFNoC Core Kernel
   //---------------------------------------------------------------------------
 
-  wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status;
+  wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
 
   rfnoc_core_kernel #(
     .PROTOVER            (PROTOVER),
     .DEVICE_TYPE         (16'hA400),
     .DEVICE_FAMILY       ("ULTRASCALE"),
     .SAFE_START_CLKS     (0),
-    .NUM_BLOCKS          (6),
-    .NUM_STREAM_ENDPOINTS(4),
+    .NUM_BLOCKS          (7),
+    .NUM_STREAM_ENDPOINTS(8),
     .NUM_ENDPOINTS_CTRL  (1),
     .NUM_TRANSPORTS      (6),
-    .NUM_EDGES           (16),
+    .NUM_EDGES           (24),
     .CHDR_XBAR_PRESENT   (1),
     .EDGE_TBL_FILE       (EDGE_TBL_FILE)
   ) core_kernel_i (
@@ -937,6 +1296,143 @@ module rfnoc_image_core #(
     .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
   );
 
+  //-----------------------------------
+  // replay0
+  //-----------------------------------
+
+  wire              replay0_mem_clk;
+  wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
+  wire              s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
+  wire              s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid;
+  wire              s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready;
+  wire [CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ;
+  wire              m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ;
+  wire              m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid;
+  wire              m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
+
+  // axi_ram
+  wire [   0:0] replay0_axi_rst;
+  wire [   3:0] replay0_m_axi_awid;
+  wire [ 191:0] replay0_m_axi_awaddr;
+  wire [  31:0] replay0_m_axi_awlen;
+  wire [  11:0] replay0_m_axi_awsize;
+  wire [   7:0] replay0_m_axi_awburst;
+  wire [   3:0] replay0_m_axi_awlock;
+  wire [  15:0] replay0_m_axi_awcache;
+  wire [  11:0] replay0_m_axi_awprot;
+  wire [  15:0] replay0_m_axi_awqos;
+  wire [  15:0] replay0_m_axi_awregion;
+  wire [   3:0] replay0_m_axi_awuser;
+  wire [   3:0] replay0_m_axi_awvalid;
+  wire [   3:0] replay0_m_axi_awready;
+  wire [2047:0] replay0_m_axi_wdata;
+  wire [ 255:0] replay0_m_axi_wstrb;
+  wire [   3:0] replay0_m_axi_wlast;
+  wire [   3:0] replay0_m_axi_wuser;
+  wire [   3:0] replay0_m_axi_wvalid;
+  wire [   3:0] replay0_m_axi_wready;
+  wire [   3:0] replay0_m_axi_bid;
+  wire [   7:0] replay0_m_axi_bresp;
+  wire [   3:0] replay0_m_axi_buser;
+  wire [   3:0] replay0_m_axi_bvalid;
+  wire [   3:0] replay0_m_axi_bready;
+  wire [   3:0] replay0_m_axi_arid;
+  wire [ 191:0] replay0_m_axi_araddr;
+  wire [  31:0] replay0_m_axi_arlen;
+  wire [  11:0] replay0_m_axi_arsize;
+  wire [   7:0] replay0_m_axi_arburst;
+  wire [   3:0] replay0_m_axi_arlock;
+  wire [  15:0] replay0_m_axi_arcache;
+  wire [  11:0] replay0_m_axi_arprot;
+  wire [  15:0] replay0_m_axi_arqos;
+  wire [  15:0] replay0_m_axi_arregion;
+  wire [   3:0] replay0_m_axi_aruser;
+  wire [   3:0] replay0_m_axi_arvalid;
+  wire [   3:0] replay0_m_axi_arready;
+  wire [   3:0] replay0_m_axi_rid;
+  wire [2047:0] replay0_m_axi_rdata;
+  wire [   7:0] replay0_m_axi_rresp;
+  wire [   3:0] replay0_m_axi_rlast;
+  wire [   3:0] replay0_m_axi_ruser;
+  wire [   3:0] replay0_m_axi_rvalid;
+  wire [   3:0] replay0_m_axi_rready;
+
+  rfnoc_block_replay #(
+    .THIS_PORTID         (8),
+    .CHDR_W              (CHDR_W),
+    .NUM_PORTS           (4),
+    .MEM_DATA_W          (64),
+    .MEM_ADDR_W          (32),
+    .MTU                 (MTU)
+  ) b_replay0_6 (
+    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
+    .mem_clk             (replay0_mem_clk),
+    .rfnoc_core_config   (rfnoc_core_config[512*7-1:512*6]),
+    .rfnoc_core_status   (rfnoc_core_status[512*7-1:512*6]),
+    .axi_rst             (replay0_axi_rst),
+    .m_axi_awid          (replay0_m_axi_awid),
+    .m_axi_awaddr        (replay0_m_axi_awaddr),
+    .m_axi_awlen         (replay0_m_axi_awlen),
+    .m_axi_awsize        (replay0_m_axi_awsize),
+    .m_axi_awburst       (replay0_m_axi_awburst),
+    .m_axi_awlock        (replay0_m_axi_awlock),
+    .m_axi_awcache       (replay0_m_axi_awcache),
+    .m_axi_awprot        (replay0_m_axi_awprot),
+    .m_axi_awqos         (replay0_m_axi_awqos),
+    .m_axi_awregion      (replay0_m_axi_awregion),
+    .m_axi_awuser        (replay0_m_axi_awuser),
+    .m_axi_awvalid       (replay0_m_axi_awvalid),
+    .m_axi_awready       (replay0_m_axi_awready),
+    .m_axi_wdata         (replay0_m_axi_wdata),
+    .m_axi_wstrb         (replay0_m_axi_wstrb),
+    .m_axi_wlast         (replay0_m_axi_wlast),
+    .m_axi_wuser         (replay0_m_axi_wuser),
+    .m_axi_wvalid        (replay0_m_axi_wvalid),
+    .m_axi_wready        (replay0_m_axi_wready),
+    .m_axi_bid           (replay0_m_axi_bid),
+    .m_axi_bresp         (replay0_m_axi_bresp),
+    .m_axi_buser         (replay0_m_axi_buser),
+    .m_axi_bvalid        (replay0_m_axi_bvalid),
+    .m_axi_bready        (replay0_m_axi_bready),
+    .m_axi_arid          (replay0_m_axi_arid),
+    .m_axi_araddr        (replay0_m_axi_araddr),
+    .m_axi_arlen         (replay0_m_axi_arlen),
+    .m_axi_arsize        (replay0_m_axi_arsize),
+    .m_axi_arburst       (replay0_m_axi_arburst),
+    .m_axi_arlock        (replay0_m_axi_arlock),
+    .m_axi_arcache       (replay0_m_axi_arcache),
+    .m_axi_arprot        (replay0_m_axi_arprot),
+    .m_axi_arqos         (replay0_m_axi_arqos),
+    .m_axi_arregion      (replay0_m_axi_arregion),
+    .m_axi_aruser        (replay0_m_axi_aruser),
+    .m_axi_arvalid       (replay0_m_axi_arvalid),
+    .m_axi_arready       (replay0_m_axi_arready),
+    .m_axi_rid           (replay0_m_axi_rid),
+    .m_axi_rdata         (replay0_m_axi_rdata),
+    .m_axi_rresp         (replay0_m_axi_rresp),
+    .m_axi_rlast         (replay0_m_axi_rlast),
+    .m_axi_ruser         (replay0_m_axi_ruser),
+    .m_axi_rvalid        (replay0_m_axi_rvalid),
+    .m_axi_rready        (replay0_m_axi_rready),
+    .s_rfnoc_chdr_tdata  ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
+    .s_rfnoc_chdr_tlast  ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
+    .s_rfnoc_chdr_tvalid ({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
+    .s_rfnoc_chdr_tready ({s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}),
+    .m_rfnoc_chdr_tdata  ({m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }),
+    .m_rfnoc_chdr_tlast  ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
+    .m_rfnoc_chdr_tvalid ({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
+    .m_rfnoc_chdr_tready ({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}),
+    .s_rfnoc_ctrl_tdata  (s_replay0_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast  (s_replay0_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready (s_replay0_ctrl_tready),
+    .m_rfnoc_ctrl_tdata  (m_replay0_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast  (m_replay0_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
+  );
+
   //---------------------------------------------------------------------------
   // Static Router
   //---------------------------------------------------------------------------
@@ -1021,6 +1517,46 @@ module rfnoc_image_core #(
   assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid;
   assign m_ddc1_out_1_tready = s_ep3_in0_tready;
 
+  assign s_replay0_in_0_tdata = m_ep4_out0_tdata;
+  assign s_replay0_in_0_tlast = m_ep4_out0_tlast;
+  assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid;
+  assign m_ep4_out0_tready = s_replay0_in_0_tready;
+
+  assign s_ep4_in0_tdata = m_replay0_out_0_tdata;
+  assign s_ep4_in0_tlast = m_replay0_out_0_tlast;
+  assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid;
+  assign m_replay0_out_0_tready = s_ep4_in0_tready;
+
+  assign s_replay0_in_1_tdata = m_ep5_out0_tdata;
+  assign s_replay0_in_1_tlast = m_ep5_out0_tlast;
+  assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid;
+  assign m_ep5_out0_tready = s_replay0_in_1_tready;
+
+  assign s_ep5_in0_tdata = m_replay0_out_1_tdata;
+  assign s_ep5_in0_tlast = m_replay0_out_1_tlast;
+  assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid;
+  assign m_replay0_out_1_tready = s_ep5_in0_tready;
+
+  assign s_replay0_in_2_tdata = m_ep6_out0_tdata;
+  assign s_replay0_in_2_tlast = m_ep6_out0_tlast;
+  assign s_replay0_in_2_tvalid = m_ep6_out0_tvalid;
+  assign m_ep6_out0_tready = s_replay0_in_2_tready;
+
+  assign s_ep6_in0_tdata = m_replay0_out_2_tdata;
+  assign s_ep6_in0_tlast = m_replay0_out_2_tlast;
+  assign s_ep6_in0_tvalid = m_replay0_out_2_tvalid;
+  assign m_replay0_out_2_tready = s_ep6_in0_tready;
+
+  assign s_replay0_in_3_tdata = m_ep7_out0_tdata;
+  assign s_replay0_in_3_tlast = m_ep7_out0_tlast;
+  assign s_replay0_in_3_tvalid = m_ep7_out0_tvalid;
+  assign m_ep7_out0_tready = s_replay0_in_3_tready;
+
+  assign s_ep7_in0_tdata = m_replay0_out_3_tdata;
+  assign s_ep7_in0_tlast = m_replay0_out_3_tlast;
+  assign s_ep7_in0_tvalid = m_replay0_out_3_tvalid;
+  assign m_replay0_out_3_tready = s_ep7_in0_tready;
+
 
   //---------------------------------------------------------------------------
   // Unused Ports
@@ -1038,6 +1574,7 @@ module rfnoc_image_core #(
   assign radio1_radio_clk = radio_clk;
   assign duc1_ce_clk = radio_2x_clk;
   assign ddc1_ce_clk = radio_2x_clk;
+  assign replay0_mem_clk = dram_clk;
 
 
   //---------------------------------------------------------------------------
@@ -1081,6 +1618,52 @@ module rfnoc_image_core #(
   assign radio1_radio_tx_stb = radio_tx_stb_radio1;
   assign radio_tx_running_radio1 = radio1_radio_tx_running;
 
+  assign replay0_axi_rst = axi_rst;
+  assign m_axi_awid = replay0_m_axi_awid;
+  assign m_axi_awaddr = replay0_m_axi_awaddr;
+  assign m_axi_awlen = replay0_m_axi_awlen;
+  assign m_axi_awsize = replay0_m_axi_awsize;
+  assign m_axi_awburst = replay0_m_axi_awburst;
+  assign m_axi_awlock = replay0_m_axi_awlock;
+  assign m_axi_awcache = replay0_m_axi_awcache;
+  assign m_axi_awprot = replay0_m_axi_awprot;
+  assign m_axi_awqos = replay0_m_axi_awqos;
+  assign m_axi_awregion = replay0_m_axi_awregion;
+  assign m_axi_awuser = replay0_m_axi_awuser;
+  assign m_axi_awvalid = replay0_m_axi_awvalid;
+  assign replay0_m_axi_awready = m_axi_awready;
+  assign m_axi_wdata = replay0_m_axi_wdata;
+  assign m_axi_wstrb = replay0_m_axi_wstrb;
+  assign m_axi_wlast = replay0_m_axi_wlast;
+  assign m_axi_wuser = replay0_m_axi_wuser;
+  assign m_axi_wvalid = replay0_m_axi_wvalid;
+  assign replay0_m_axi_wready = m_axi_wready;
+  assign replay0_m_axi_bid = m_axi_bid;
+  assign replay0_m_axi_bresp = m_axi_bresp;
+  assign replay0_m_axi_buser = m_axi_buser;
+  assign replay0_m_axi_bvalid = m_axi_bvalid;
+  assign m_axi_bready = replay0_m_axi_bready;
+  assign m_axi_arid = replay0_m_axi_arid;
+  assign m_axi_araddr = replay0_m_axi_araddr;
+  assign m_axi_arlen = replay0_m_axi_arlen;
+  assign m_axi_arsize = replay0_m_axi_arsize;
+  assign m_axi_arburst = replay0_m_axi_arburst;
+  assign m_axi_arlock = replay0_m_axi_arlock;
+  assign m_axi_arcache = replay0_m_axi_arcache;
+  assign m_axi_arprot = replay0_m_axi_arprot;
+  assign m_axi_arqos = replay0_m_axi_arqos;
+  assign m_axi_arregion = replay0_m_axi_arregion;
+  assign m_axi_aruser = replay0_m_axi_aruser;
+  assign m_axi_arvalid = replay0_m_axi_arvalid;
+  assign replay0_m_axi_arready = m_axi_arready;
+  assign replay0_m_axi_rid = m_axi_rid;
+  assign replay0_m_axi_rdata = m_axi_rdata;
+  assign replay0_m_axi_rresp = m_axi_rresp;
+  assign replay0_m_axi_rlast = m_axi_rlast;
+  assign replay0_m_axi_ruser = m_axi_ruser;
+  assign replay0_m_axi_rvalid = m_axi_rvalid;
+  assign m_axi_rready = replay0_m_axi_rready;
+
   // Broadcaster/Listener Connections:
   assign radio0_radio_time = radio_time;
 
diff --git a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh
index 3ba2707d4..8d9e8af8b 100644
--- a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -12,9 +12,9 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:46:07.744077
-// Source: x410_200_rfnoc_image_core.yml
-// Source SHA256: e841d2a58556840a822f9398b8888cc871bf0473c364bcdcb0f46ffce88224c9
+// File generated on: 2022-02-02T14:39:11.410399
+// Source: ./x410_200_rfnoc_image_core.yml
+// Source SHA256: 57ca44ee7facd8ddcd6a88170463ea9665328e011511c8b5d87684fc78b43bd6
 //
 
 `define CHDR_WIDTH     64
diff --git a/fpga/usrp3/top/x400/x410_200_static_router.hex b/fpga/usrp3/top/x400/x410_200_static_router.hex
index 73449b968..99d1452cd 100644
--- a/fpga/usrp3/top/x400/x410_200_static_router.hex
+++ b/fpga/usrp3/top/x400/x410_200_static_router.hex
@@ -1,17 +1,25 @@
-00000010
-00400140
-014001c0
-01c00180
-01800040
-00800141
-014101c1
-01c10181
-01810080
-00c00200
-02000280
-02800240
-024000c0
-01000201
-02010281
-02810241
-02410100
+00000018
+00400240
+024002c0
+02c00280
+02800040
+00800241
+024102c1
+02c10281
+02810080
+00c00300
+03000380
+03800340
+034000c0
+01000301
+03010381
+03810341
+03410100
+014003c0
+03c00140
+018003c1
+03c10180
+01c003c2
+03c201c0
+020003c3
+03c30200
diff --git a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v
index e1a7aa1f9..0d14ecc97 100644
--- a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -13,7 +13,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:46:11.559326
+// File generated on: 2022-01-24T08:37:29.737428
 // Source: x410_400_rfnoc_image_core.yml
 // Source SHA256: aff421903b98211e4822bd2968fd02c679bf30a215ee65e906d4f9a1d79df71e
 //
@@ -33,6 +33,7 @@ module rfnoc_image_core #(
   input  wire         core_arst,
   input  wire         radio_clk,
   input  wire         radio_2x_clk,
+  input  wire         dram_clk,
   // Basic
   input  wire [  15:0] device_id,
 
@@ -76,6 +77,52 @@ module rfnoc_image_core #(
   output wire [ 255:0] radio_tx_data_radio1,
   input  wire [   7:0] radio_tx_stb_radio1,
   output wire [   7:0] radio_tx_running_radio1,
+  // dram
+  input  wire [   0:0] axi_rst,
+  output wire [   3:0] m_axi_awid,
+  output wire [ 191:0] m_axi_awaddr,
+  output wire [  31:0] m_axi_awlen,
+  output wire [  11:0] m_axi_awsize,
+  output wire [   7:0] m_axi_awburst,
+  output wire [   3:0] m_axi_awlock,
+  output wire [  15:0] m_axi_awcache,
+  output wire [  11:0] m_axi_awprot,
+  output wire [  15:0] m_axi_awqos,
+  output wire [  15:0] m_axi_awregion,
+  output wire [   3:0] m_axi_awuser,
+  output wire [   3:0] m_axi_awvalid,
+  input  wire [   3:0] m_axi_awready,
+  output wire [2047:0] m_axi_wdata,
+  output wire [ 255:0] m_axi_wstrb,
+  output wire [   3:0] m_axi_wlast,
+  output wire [   3:0] m_axi_wuser,
+  output wire [   3:0] m_axi_wvalid,
+  input  wire [   3:0] m_axi_wready,
+  input  wire [   3:0] m_axi_bid,
+  input  wire [   7:0] m_axi_bresp,
+  input  wire [   3:0] m_axi_buser,
+  input  wire [   3:0] m_axi_bvalid,
+  output wire [   3:0] m_axi_bready,
+  output wire [   3:0] m_axi_arid,
+  output wire [ 191:0] m_axi_araddr,
+  output wire [  31:0] m_axi_arlen,
+  output wire [  11:0] m_axi_arsize,
+  output wire [   7:0] m_axi_arburst,
+  output wire [   3:0] m_axi_arlock,
+  output wire [  15:0] m_axi_arcache,
+  output wire [  11:0] m_axi_arprot,
+  output wire [  15:0] m_axi_arqos,
+  output wire [  15:0] m_axi_arregion,
+  output wire [   3:0] m_axi_aruser,
+  output wire [   3:0] m_axi_arvalid,
+  input  wire [   3:0] m_axi_arready,
+  input  wire [   3:0] m_axi_rid,
+  input  wire [2047:0] m_axi_rdata,
+  input  wire [   7:0] m_axi_rresp,
+  input  wire [   3:0] m_axi_rlast,
+  input  wire [   3:0] m_axi_ruser,
+  input  wire [   3:0] m_axi_rvalid,
+  output wire [   3:0] m_axi_rready,
 
   // Transport Adapters ///////////////
 
diff --git a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh
index da7e01f79..8b6311c0f 100644
--- a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
 //
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -12,7 +12,7 @@
 //   This file was automatically generated by the RFNoC image builder tool.
 //   Re-running that tool will overwrite this file!
 //
-// File generated on: 2021-05-03T08:46:11.605928
+// File generated on: 2022-01-24T08:37:29.769622
 // Source: x410_400_rfnoc_image_core.yml
 // Source SHA256: aff421903b98211e4822bd2968fd02c679bf30a215ee65e906d4f9a1d79df71e
 //