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| author | RobertWalstab <robert.walstab@gmail.com> | 2020-07-24 16:31:45 +0200 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-07-24 15:24:14 -0500 |
| commit | 54d698e3707cf1be5d38537db783ebadd850e729 (patch) | |
| tree | fbe89e9fb713412dd1016131bec7baffbc664163 | |
| parent | 5023e66b2dc46730f66f3c471fcfe0fc6bbf1200 (diff) | |
| download | uhd-54d698e3707cf1be5d38537db783ebadd850e729.tar.gz uhd-54d698e3707cf1be5d38537db783ebadd850e729.tar.bz2 uhd-54d698e3707cf1be5d38537db783ebadd850e729.zip | |
fpga, mpm: Bump FPGA compat number
| -rw-r--r-- | fpga/usrp3/top/e31x/e31x_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/e320/e320_core.v | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n3xx_core.v | 2 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e31x.py | 2 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e320.py | 2 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx.py | 2 |
6 files changed, 6 insertions, 6 deletions
diff --git a/fpga/usrp3/top/e31x/e31x_core.v b/fpga/usrp3/top/e31x/e31x_core.v index 8037b886b..6e4283285 100644 --- a/fpga/usrp3/top/e31x/e31x_core.v +++ b/fpga/usrp3/top/e31x/e31x_core.v @@ -126,7 +126,7 @@ module e31x_core #( // ///////////////////////////////////////////////////////////////////////////////// - localparam [15:0] COMPAT_MAJOR = 16'd5; + localparam [15:0] COMPAT_MAJOR = 16'd6; localparam [15:0] COMPAT_MINOR = 16'd0; ///////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp3/top/e320/e320_core.v b/fpga/usrp3/top/e320/e320_core.v index e65e63314..f9cadee89 100644 --- a/fpga/usrp3/top/e320/e320_core.v +++ b/fpga/usrp3/top/e320/e320_core.v @@ -190,7 +190,7 @@ module e320_core #( // ///////////////////////////////////////////////////////////////////////////////// - localparam [15:0] COMPAT_MAJOR = 16'd5; + localparam [15:0] COMPAT_MAJOR = 16'd6; localparam [15:0] COMPAT_MINOR = 16'd0; ///////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp3/top/n3xx/n3xx_core.v b/fpga/usrp3/top/n3xx/n3xx_core.v index af9edcd68..5128d57f7 100644 --- a/fpga/usrp3/top/n3xx/n3xx_core.v +++ b/fpga/usrp3/top/n3xx/n3xx_core.v @@ -209,7 +209,7 @@ module n3xx_core #( // ///////////////////////////////////////////////////////////////////////////////// - localparam [15:0] COMPAT_MAJOR = 16'd7; + localparam [15:0] COMPAT_MAJOR = 16'd8; localparam [15:0] COMPAT_MINOR = 16'd0; ///////////////////////////////////////////////////////////////////////////////// diff --git a/mpm/python/usrp_mpm/periph_manager/e31x.py b/mpm/python/usrp_mpm/periph_manager/e31x.py index 8043fc704..11f65dd17 100644 --- a/mpm/python/usrp_mpm/periph_manager/e31x.py +++ b/mpm/python/usrp_mpm/periph_manager/e31x.py @@ -31,7 +31,7 @@ E310_DEFAULT_CLOCK_SOURCE = 'internal' E310_DEFAULT_TIME_SOURCE = 'internal' E310_DEFAULT_ENABLE_FPGPIO = True E310_DEFAULT_DONT_RELOAD_FPGA = False # False means idle image gets reloaded -E310_FPGA_COMPAT = (5, 0) +E310_FPGA_COMPAT = (6, 0) E310_DBOARD_SLOT_IDX = 0 E310_GPIO_SRC_PS = "PS" # We use the index positions of RFA and RFB to map between name and radio index diff --git a/mpm/python/usrp_mpm/periph_manager/e320.py b/mpm/python/usrp_mpm/periph_manager/e320.py index dc91b20d9..770b449b5 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320.py +++ b/mpm/python/usrp_mpm/periph_manager/e320.py @@ -32,7 +32,7 @@ E320_DEFAULT_CLOCK_SOURCE = 'internal' E320_DEFAULT_TIME_SOURCE = 'internal' E320_DEFAULT_ENABLE_GPS = True E320_DEFAULT_ENABLE_FPGPIO = True -E320_FPGA_COMPAT = (5, 0) +E320_FPGA_COMPAT = (6, 0) E320_MONITOR_THREAD_INTERVAL = 1.0 # seconds E320_DBOARD_SLOT_IDX = 0 E320_GPIO_BANKS = ["FP0",] diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py index e73fb81db..7a9f61df7 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py @@ -41,7 +41,7 @@ N3XX_DEFAULT_ENABLE_PPS_EXPORT = True N32X_DEFAULT_QSFP_RATE_PRESET = 'Ethernet' N32X_DEFAULT_QSFP_DRIVER_PRESET = 'Optical' N32X_QSFP_I2C_LABEL = 'qsfp-i2c' -N3XX_FPGA_COMPAT = (7, 0) +N3XX_FPGA_COMPAT = (8, 0) N3XX_MONITOR_THREAD_INTERVAL = 1.0 # seconds N3XX_BUS_CLK = 200e6 N3XX_GPIO_BANKS = ["FP0",] |