docs: Fix page on GPIO

- Referred to E310 as E3x0, but that's wrong. E320 has a different GPIO
  bank naming scheme.
- Fails to mention N3x0. This change makes the page mostly
  device-agnostic (X410 GPIO control is still elsewhere).
- The first example had a typo (wrong pin was selected in ATR example).
- The second example added nothing, and was removed for clarity.

2 files changed, 21 insertions, 52 deletions

diff --git a/host/docs/gpio_api.dox b/host/docs/gpio_api.dox
index 8617000ad..82e5fa253 100644
--- a/host/docs/gpio_api.dox
+++ b/host/docs/gpio_api.dox
@@ -1,10 +1,10 @@
-/*! \page page_gpio_api E3x0/X3x0 GPIO API
+/*! \page page_gpio_api GPIO API
 
 \tableofcontents
 
-\section xgpio_fpanel The E3x0/X3x0 Front Panel GPIO
+\section xgpio_fpanel The Front Panel GPIO
 
-The E3x0/X3x0 are the first USRP devices to offer an auxiliary GPIO connection
+All Generation-3 USRP offer an auxiliary GPIO connection
 on the motherboard itself (independent of the daughterboards). These
 GPIO pins are controlled directly by the FPGA, where they are controlled
 by an ATR (Automatic Transmit / Receive). This allows them to be toggled
@@ -106,12 +106,13 @@ one more:
 \subsection xgpio_fpanel_xample An Example
 
 The front panel X3x0 GPIO bank is enumerated in the motherboard property
-tree (`<mb_path>/gpio/FP0/\*`), the E3x0 internal GPIO bank as (`<mb_path>/gpio/INT0/\`) and so are easily accessible through
-the standard uhd::usrp::multi_usrp UHD interface.
+tree (`<mb_path>/gpio/FP0/\*`), the E31x internal GPIO bank as (`<mb_path>/gpio/INT0/\`)
+and so are easily accessible through the standard uhd::usrp::multi_usrp UHD interface.
 
 You can discover this using the uhd::usrp::multi_usrp::get_gpio_banks() function.
-This will tell you that there is a GPIO bank on your
-X3x0 called "FP0" (for E3x0 this will be called "INT0"). This is the bank we want to set-up.
+This will tell you that there is a GPIO bank on your X3x0, E320, or N3x0 called
+"FP0" (for E31x this will be called "INT0").
+This is the bank we want to set up.
 
 Let's say we want to use GPIO6 for an external amp. We want it to be
 automatically controlled by ATR as an output, and we want it to be high
@@ -132,62 +133,30 @@ up with the following code:
     // set up the GPIO directions: 1 for output, 0 for input
     #define GPIO_DDR        (AMP_GPIO_MASK | MAN_GPIO_MASK)
 
-    // assume an existing USRP device handle, called "usrp_x300"
+    // assume an existing multi_usrp object, called "usrp"
 
     // now, let's do the basic ATR setup
-    usrp_x300->set_gpio_attr("FP0", "CTRL", ATR_CONTROL, ATR_MASKS);
-    usrp_x300->set_gpio_attr("FP0", "DDR", GPIO_DDR, ATR_MASKS);
+    usrp->set_gpio_attr("FP0", "CTRL", ATR_CONTROL, ATR_MASKS);
+    usrp->set_gpio_attr("FP0", "DDR", GPIO_DDR, ATR_MASKS);
 
     // let's manually set GPIO4 high
-    usrp_x300->set_gpio_attr("FP0", "OUT", 1, MAN_GPIO_MASK);
+    usrp->set_gpio_attr("FP0", "OUT", 1, MAN_GPIO_MASK);
 
     // finally, let's set up GPIO6 as we described above
-    usrp_x300->set_gpio_attr("FP0", "ATR_0X", 0, AMP_GPIO_MASK);
-    usrp_x300->set_gpio_attr("FP0", "ATR_RX", 0, AMP_GPIO_MASK);
-    usrp_x300->set_gpio_attr("FP0", "ATR_TX", (1 << 3), AMP_GPIO_MASK);
-    usrp_x300->set_gpio_attr("FP0", "ATR_XX", 0, AMP_GPIO_MASK);
+    usrp->set_gpio_attr("FP0", "ATR_0X", 0, AMP_GPIO_MASK);
+    usrp->set_gpio_attr("FP0", "ATR_RX", 0, AMP_GPIO_MASK);
+    usrp->set_gpio_attr("FP0", "ATR_TX", AMP_GPIO_MASK, AMP_GPIO_MASK);
+    // usually, you would want to also make this pin go high when doing
+    // full-duplex, but not in this example
+    usrp->set_gpio_attr("FP0", "ATR_XX", 0, AMP_GPIO_MASK);
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 After the above code is run, the ATR in the FPGA will automatically
 control GPIO6, as we have described, based on the radio state, and we
 have direct manual control over GPIO4.
 
-The following example has been modified to work with he E3x0's internal
-GPIO bank, where the controlled GPIO is now GPIO3 instead of GPIO6.
-
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp}
-    // set up our masks, defining the pin numbers
-    #define AMP_GPIO_MASK   (1 << 3)
-    #define MAN_GPIO_MASK   (1 << 4)
-
-    #define ATR_MASKS       (AMP_GPIO_MASK | MAN_GPIO_MASK)
-
-    // set up our values for ATR control: 1 for ATR, 0 for manual
-    #define ATR_CONTROL     (AMP_GPIO_MASK & ~MAN_GPIO_MASK)
-
-    // set up the GPIO directions: 1 for output, 0 for input
-    #define GPIO_DDR        (AMP_GPIO_MASK & ~MAN_GPIO_MASK)
-
-    // assume an existing USRP device handle, called "usrp_e300"
-
-    // now, let's do the basic ATR setup
-    usrp_e300->set_gpio_attr("INT0", "CTRL", ATR_CONTROL, ATR_MASKS);
-    usrp_e300->set_gpio_attr("INT0", "DDR", GPIO_DDR, ATR_MASKS);
-
-    // let's manually set GPIO4 high
-    usrp_e300->set_gpio_attr("INT0", "OUT", (1 << 4), MAN_GPIO_MASK);
-
-    // finally, let's set up GPIO3 as we described above
-    usrp_e300->set_gpio_attr("INT0", "ATR_0X", 0, AMP_GPIO_MASK);
-    usrp_e300->set_gpio_attr("INT0", "ATR_RX", 0, AMP_GPIO_MASK);
-    usrp_e300->set_gpio_attr("INT0", "ATR_TX", (1 << 3), AMP_GPIO_MASK);
-    usrp_e300->set_gpio_attr("INT0", "ATR_XX", 0, AMP_GPIO_MASK);
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-After the above code is run, the ATR in the FPGA will automatically
-control GPIO3, as we have described, based on the radio state, and we
-have direct manual control over GPIO4.
-
+To modify the example to work with the E31x's internal GPIO bank, use the bank
+name "INT0" instead of "FP0".
 
 */
 // vim:ft=doxygen:
diff --git a/host/docs/usrp_e3xx.dox b/host/docs/usrp_e3xx.dox
index 368cff34b..b51a31ab6 100644
--- a/host/docs/usrp_e3xx.dox
+++ b/host/docs/usrp_e3xx.dox
@@ -1042,7 +1042,7 @@ of your device. Note that this supply voltage is turned off in order to safe pow
 
 ### Connector
 
-\image html e3x0_gpio_conn.png "E3xx GPIO Connector"
+\image html e3x0_gpio_conn.png "E31x GPIO Connector"
 
 ### Pin Mapping