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| author | Wade Fife <wade.fife@ettus.com> | 2022-01-26 12:13:59 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-02-07 13:08:11 -0700 |
| commit | 26372c19a9ae32956954b4ed72bddc58f54c9c18 (patch) | |
| tree | d5382e342e3905cd8d85f7b60302c1349f224e24 | |
| parent | 5122ce9a399a5ba9c20293385ccef89e23ec3926 (diff) | |
| download | uhd-26372c19a9ae32956954b4ed72bddc58f54c9c18.tar.gz uhd-26372c19a9ae32956954b4ed72bddc58f54c9c18.tar.bz2 uhd-26372c19a9ae32956954b4ed72bddc58f54c9c18.zip | |
fpga: ci: Increase PR pipeline timeout
| -rw-r--r-- | fpga/.ci/x4xx-pr-check.yml | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/fpga/.ci/x4xx-pr-check.yml b/fpga/.ci/x4xx-pr-check.yml index 3de9f674d..c1a26edf9 100644 --- a/fpga/.ci/x4xx-pr-check.yml +++ b/fpga/.ci/x4xx-pr-check.yml @@ -36,7 +36,7 @@ jobs: target: X410_XG_100 debug: true # to be able to debug any failed attempts clean: false # for speedup of PR testing - timeout: 360 + timeout: 480 # ------------------------------------------------------------------- # Build X4 FPGA (200 MHz) @@ -46,7 +46,7 @@ jobs: target: X410_X4_200 debug: true # to be able to debug any failed attempts clean: false # for speedup of PR testing - timeout: 360 + timeout: 480 # ------------------------------------------------------------------- # Build C1 FPGA (400 MHz) @@ -56,7 +56,7 @@ jobs: target: X410_C1_400 debug: true # to be able to debug any failed attempts clean: false # for speedup of PR testing - timeout: 360 + timeout: 480 # ------------------------------------------------------------------- # Make CPLD |