mpm: mg: Make set_master_clock_rate() an async call

The ad9371 call set_master_clock_rate() can take a while depending on
the rate change, so make it asynchronous in order not to lock out the
reclaimer loop.

2 files changed, 17 insertions, 2 deletions

diff --git a/mpm/include/mpm/ad937x/ad937x_ctrl.hpp b/mpm/include/mpm/ad937x/ad937x_ctrl.hpp
index cb4d0e060..44e814e60 100644
--- a/mpm/include/mpm/ad937x/ad937x_ctrl.hpp
+++ b/mpm/include/mpm/ad937x/ad937x_ctrl.hpp
@@ -86,6 +86,7 @@ public:
     std::future<void> handle_finish_initialization;
     std::future<void> handle_setup_cal;
     std::future<double> handle_set_freq;
+    std::future<void> handle_set_master_clock_rate;
 
     /*! \brief make a new AD9371 ctrl object using the specified SPI iface
      *
@@ -283,6 +284,20 @@ void export_mykonos(py::module& top_module)
 
     py::class_<ad937x_ctrl, std::shared_ptr<ad937x_ctrl>>(m, "ad937x_ctrl")
         .def("set_master_clock_rate", &ad937x_ctrl::set_master_clock_rate)
+        .def("async__set_master_clock_rate",
+            +[](ad937x_ctrl& self, const double rate) {
+                self.handle_set_master_clock_rate = std::async(std::launch::async,
+                    [&self, rate]() { self.set_master_clock_rate(rate); });
+            })
+        .def("await__set_master_clock_rate",
+            +[](ad937x_ctrl& self) -> bool {
+                if (self.handle_set_master_clock_rate.wait_for(std::chrono::seconds(0))
+                    == std::future_status::ready) {
+                    self.handle_set_master_clock_rate.get();
+                    return true;
+                }
+                return false;
+            })
         .def("begin_initialization", &ad937x_ctrl::begin_initialization)
         .def("async__finish_initialization",
             +[](ad937x_ctrl& self) {
diff --git a/mpm/python/usrp_mpm/dboard_manager/mg_init.py b/mpm/python/usrp_mpm/dboard_manager/mg_init.py
index d2b597c21..5bd2d217a 100644
--- a/mpm/python/usrp_mpm/dboard_manager/mg_init.py
+++ b/mpm/python/usrp_mpm/dboard_manager/mg_init.py
@@ -556,8 +556,8 @@ class MagnesiumInitManager(object):
             self.log.debug(
                 "Sample Clocks and Phase DAC Configured Successfully!")
             # Clocks and PPS are now fully active!
-            if args.get('skip_rfic', None) == None:
-                self.mykonos.set_master_clock_rate(master_clock_rate)
+            if args.get('skip_rfic', None) is None:
+                async_exec(self.mykonos, "set_master_clock_rate", master_clock_rate)
                 self.init_jesd(jesdcore, master_clock_rate, args)
             jesdcore = None # Help with garbage collection
             # That's all that requires access to the dboard regs!