diff options
| author | Matt Ettus <matt@ettus.com> | 2011-01-06 12:41:33 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-07 14:42:58 -0700 |
| commit | e2eca54dafc2f9040485d3f5658ce97dad66aa2b (patch) | |
| tree | 3016eb8876877c9e9a061d8b5c6366c485ac1cf8 | |
| parent | e7eb44d5abc1021972c07c4b867c98c8223eca2b (diff) | |
| download | uhd-e2eca54dafc2f9040485d3f5658ce97dad66aa2b.tar.gz uhd-e2eca54dafc2f9040485d3f5658ce97dad66aa2b.tar.bz2 uhd-e2eca54dafc2f9040485d3f5658ce97dad66aa2b.zip | |
builds now
| -rw-r--r-- | usrp2/top/u2plus/Makefile | 1 | ||||
| -rw-r--r-- | usrp2/top/u2plus/capture_ddrlvds.v | 5 |
2 files changed, 4 insertions, 2 deletions
diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile index 38400ce62..ed044d6a8 100644 --- a/usrp2/top/u2plus/Makefile +++ b/usrp2/top/u2plus/Makefile @@ -45,6 +45,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ +capture_ddrlvds.v \ u2plus_core.v \ u2plus.v \ u2plus.ucf diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v index ff1b586e2..65635750e 100644 --- a/usrp2/top/u2plus/capture_ddrlvds.v +++ b/usrp2/top/u2plus/capture_ddrlvds.v @@ -16,13 +16,14 @@ module capture_ddrlvds wire [(2*WIDTH)-1:0] out_pre1; reg [(2*WIDTH)-1:0] out_pre2; - IBUFGDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("FALSE")) + clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); genvar i; generate for(i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins - IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) ibufds + IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), |