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| author | Matt Ettus <matt@ettus.com> | 2011-03-25 15:55:50 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:21 -0700 |
| commit | 9fe534886ce3515b08aca53cae5dff336e53147e (patch) | |
| tree | e42d66fedc8c1869e643646db212e0f8f671af3e | |
| parent | b8f5df998505727321cd23d04d23a89fd616cb9c (diff) | |
| download | uhd-9fe534886ce3515b08aca53cae5dff336e53147e.tar.gz uhd-9fe534886ce3515b08aca53cae5dff336e53147e.tar.bz2 uhd-9fe534886ce3515b08aca53cae5dff336e53147e.zip | |
u1p: debug pins
| -rw-r--r-- | usrp2/gpif/gpif.v | 4 | ||||
| -rw-r--r-- | usrp2/top/u1plus/u1plus_core.v | 5 | ||||
| -rw-r--r-- | usrp2/vrt/vita_rx_control.v | 6 |
3 files changed, 9 insertions, 6 deletions
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 4f0ed233b..052a66bff 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -220,7 +220,9 @@ module gpif // //////////////////////////////////////////// // DEBUG - assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; + assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], + gpif_d_copy[15:0] }; + assign debug1 = { { debug_rd[15:8] }, { debug_rd[7:0] }, { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index f50d71c81..167f0d6b9 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -331,7 +331,7 @@ module u1plus_core .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); + .gpio( /*{io_tx,io_rx}*/ ) ); // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #8 + 9 @@ -389,6 +389,7 @@ module u1plus_core assign debug = debug0; assign debug_gpio_0 = 0; assign debug_gpio_1 = 0; - + assign {io_tx,io_rx} = vrc_debug | vrf_debug; + endmodule // u1plus_core diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 4c0cef50d..73d9b87fd 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -191,9 +191,9 @@ module vita_rx_control assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) & not_empty_ctrl; - assign debug_rx = { { ibs_state[2:0], command_queue_len }, + assign debug_rx = { { 8'd0 }, { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, - { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; + { go_now, too_late, run, strobe, read_ctrl, write_ctrl, overrun, ~not_empty_ctrl }, + { ibs_state[2:0], chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // vita_rx_control |