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| author | Matt Ettus <matt@ettus.com> | 2010-09-22 19:05:10 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:19 -0700 |
| commit | 955572c4ad4866202256fed4c7200ac14106e079 (patch) | |
| tree | a2799c46811b64bf460f4f7ff36a79a594e9b4e1 | |
| parent | af9c419ec95c665b9f7921957115c870aea0ce46 (diff) | |
| download | uhd-955572c4ad4866202256fed4c7200ac14106e079.tar.gz uhd-955572c4ad4866202256fed4c7200ac14106e079.tar.bz2 uhd-955572c4ad4866202256fed4c7200ac14106e079.zip | |
constrain the gpif clock
| -rw-r--r-- | usrp2/top/u1plus/timing.ucf | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/usrp2/top/u1plus/timing.ucf b/usrp2/top/u1plus/timing.ucf index ca5ebf8e3..b2a455f6d 100644 --- a/usrp2/top/u1plus/timing.ucf +++ b/usrp2/top/u1plus/timing.ucf @@ -1,2 +1,5 @@ NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; |