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authorMartin Braun <martin.braun@ettus.com>2019-02-26 16:20:48 -0800
committerMichael West <michael.west@ettus.com>2019-03-05 10:33:21 -0800
commit75236de2ee8c7ea4df8d2511b1df7dc24a8de91a (patch)
tree7cea7ec205447e65bfa60d496abc7e028f57ccce
parentdd61c2376f62b42e06844fd23522138eb7c01a04 (diff)
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docs: x300: Add notes on external reference frequencies
-rw-r--r--host/docs/configuration.dox1
-rw-r--r--host/docs/usrp_x3x0.dox13
2 files changed, 12 insertions, 2 deletions
diff --git a/host/docs/configuration.dox b/host/docs/configuration.dox
index ccc3129fb..480410d5c 100644
--- a/host/docs/configuration.dox
+++ b/host/docs/configuration.dox
@@ -28,6 +28,7 @@ and possible more options.
ignore-cal-file | Ignores existing device calibration files | All Devices with cal-file support| See \ref ignore_cal_file
master_clock_rate | Master Clock Rate in Hz | X3x0, B2x0, B1x0, E3x0, E1x0, N3xx | master_clock_rate=16e6
dboard_clock_rate | Daughterboard clock rate in Hz | X3x0 | dboard_clock_rate=50e6
+ system_ref_rate | Frequency of external reference | X3x0 | system_ref_rate=11.52e6
mcr | Override master clock rate settings (see \ref usrp1_hw_extclk) | USRP1 | mcr=52e6
niusrprpc_port | RPC Port for NI USRP RIO | X3x0 | niusrprpc_port=5445
system_ref_rate | Reference Clock Rate in Hz | X3x0 | system_ref_rate=10e6
diff --git a/host/docs/usrp_x3x0.dox b/host/docs/usrp_x3x0.dox
index e8d1af24e..d55643e1f 100644
--- a/host/docs/usrp_x3x0.dox
+++ b/host/docs/usrp_x3x0.dox
@@ -15,7 +15,7 @@ More information:
- Dual SFP+ Transceivers (can be used with 1 GigE, 10 GigE)
- PCI Express over cable (MXI) gen1 x4
- External PPS input & output
- - External 10 MHz input & output
+ - External reference (10 MHz, 11.52 MHz, 23.04 MHz, or 30.72 MHz) input & output
- Expandable via 2nd SFP+ interface
- Supported master clock rates: 200 MHz and 184.32 MHz
- Variable daughterboard clock rates
@@ -663,12 +663,21 @@ Afterward, power-cycle your X-Series device for the changes to take effect.
- **PPS/TRIG IN**: Input port for the PPS signal
- **GPS**: Connection for the GPS antenna
-\subsection x3x0_hw_x3x0_hw_ref10M Ref Clock - 10 MHz
+\subsection x3x0_hw_x3x0_hw_ref10M Ref Clock (10 MHz or other frequency)
Using an external 10 MHz reference clock, a square wave will offer the best phase
noise performance, but a sinusoid is acceptable.
The power level of the reference clock must exceed +15 dBm.
+The following reference frequencies are supported:
+- 10 MHz
+- 11.52 MHz
+- 23.04 MHz
+- 30.72 MHz
+
+If the external reference clock is not 10 MHz, the `system_ref_rate` device arg
+must be provided.
+
To use the external reference in your UHD session, make sure to either call
uhd::usrp::multi_usrp::set_clock_source() or specify `clock_source=external` in
your device args.