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| author | Ian Buckley <ian.buckley@gmail.com> | 2015-05-26 15:35:04 -0700 |
|---|---|---|
| committer | Ian Buckley <ianb@ionconcepts.com> | 2015-07-08 11:51:25 -0700 |
| commit | 69bcfba936e49c2825a6d9be677c3150a5c6b70c (patch) | |
| tree | eba7afc1762bf1f3e6a23d3d81092560625cfb4b | |
| parent | 22fedfc3a656eca181f8bba6ffcec680e6c300e4 (diff) | |
| download | uhd-69bcfba936e49c2825a6d9be677c3150a5c6b70c.tar.gz uhd-69bcfba936e49c2825a6d9be677c3150a5c6b70c.tar.bz2 uhd-69bcfba936e49c2825a6d9be677c3150a5c6b70c.zip | |
B200: New AD9361 I/O timing programming to work with new b200_io.v logic design.
| -rw-r--r-- | host/lib/usrp/b200/b200_impl.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/common/ad9361_driver/ad9361_device.cpp | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/host/lib/usrp/b200/b200_impl.cpp b/host/lib/usrp/b200/b200_impl.cpp index 55ae29575..0409adf30 100644 --- a/host/lib/usrp/b200/b200_impl.cpp +++ b/host/lib/usrp/b200/b200_impl.cpp @@ -63,7 +63,7 @@ public: digital_interface_delays_t get_digital_interface_timing() { digital_interface_delays_t delays; delays.rx_clk_delay = 0; - delays.rx_data_delay = 0x6; + delays.rx_data_delay = 0xF; delays.tx_clk_delay = 0; delays.tx_data_delay = 0xF; return delays; diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp index e63460730..db5de52d0 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp @@ -1455,13 +1455,13 @@ void ad9361_device_t::initialize() * Force TX on one port, RX on the other. */ switch (_client_params->get_digital_interface_mode()) { case AD9361_DDR_FDD_LVCMOS: { - _io_iface->poke8(0x010, 0xc8); + _io_iface->poke8(0x010, 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode _io_iface->poke8(0x011, 0x00); _io_iface->poke8(0x012, 0x02); } break; case AD9361_DDR_FDD_LVDS: { - _io_iface->poke8(0x010, 0xcc); + _io_iface->poke8(0x010, 0xcc); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode, 2R2T timing. _io_iface->poke8(0x011, 0x00); _io_iface->poke8(0x012, 0x10); |