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| author | mguyler-ni <mark.guyler@ni.com> | 2019-02-26 17:43:34 -0800 |
|---|---|---|
| committer | Michael West <michael.west@ettus.com> | 2019-03-05 10:34:06 -0800 |
| commit | 5b29b95de8219e8da26fd6c3e2b4a735caaf4374 (patch) | |
| tree | 73652fd8b61a6cfc6fefc94df42266e665a2bed7 | |
| parent | 95b84163f448eb942590071b02b57569a2f3e5fd (diff) | |
| download | uhd-5b29b95de8219e8da26fd6c3e2b4a735caaf4374.tar.gz uhd-5b29b95de8219e8da26fd6c3e2b4a735caaf4374.tar.bz2 uhd-5b29b95de8219e8da26fd6c3e2b4a735caaf4374.zip | |
x300: Change PLL CP currents in x300_clock_ctrl
- modify PLL charge pump values to improve phase coherence
- affects reference clocks of 11.52 MHz, 23.04 MHz, and 30.72 MHz
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index a867a9138..9b54b001b 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -699,13 +699,13 @@ private: // PLL1 - 2 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 48; _lmk04816_regs.PLL1_R_27 = 5; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 7.68 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 168; _lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A; _lmk04816_regs.PLL2_R_28 = 25; - _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA; + _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA; _lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_4KILO_OHM; _lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF; @@ -722,13 +722,13 @@ private: // PLL1 - 1.92 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 6; _lmk04816_regs.PLL1_R_27 = 6; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 7.68 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 168; _lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A; _lmk04816_regs.PLL2_R_28 = 25; - _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA; + _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA; _lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_1KILO_OHM; _lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF; @@ -745,13 +745,13 @@ private: // PLL1 - 1.92 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 12; _lmk04816_regs.PLL1_R_27 = 12; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 7.68 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 168; _lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A; _lmk04816_regs.PLL2_R_28 = 25; - _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA; + _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA; _lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_1KILO_OHM; _lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF; @@ -768,13 +768,13 @@ private: // PLL1 - 2.048 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 15; _lmk04816_regs.PLL1_R_27 = 15; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 7.68 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 168; _lmk04816_regs.PLL2_P_30 = lmk04816_regs_t::PLL2_P_30_DIV_2A; _lmk04816_regs.PLL2_R_28 = 25; - _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_3200UA; + _lmk04816_regs.PLL2_CP_GAIN_26 = lmk04816_regs_t::PLL2_CP_GAIN_26_100UA; _lmk04816_regs.PLL2_R3_LF = lmk04816_regs_t::PLL2_R3_LF_1KILO_OHM; _lmk04816_regs.PLL2_C3_LF = lmk04816_regs_t::PLL2_C3_LF_39PF; |