ad9361: Fix return values for tune and set_clock_rate

This fixes a potential mismatch between the returned frequency and
clock rate and the actual value. The new function get_clock_rate is
need for async call to set_clock_rate in E3xx devices

2 files changed, 11 insertions, 3 deletions

diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
index 16bcadd2d..f0e10871e 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
@@ -1911,10 +1911,15 @@ double ad9361_device_t::set_clock_rate(const double req_rate)
         break;
     };
 
-    return rate;
+    return get_clock_rate();
 }
 
-
+/* This function returns the RX / TX rate between AD9361 and the FPGA.
+ */
+double ad9361_device_t::get_clock_rate()
+{
+    return _baseband_bw;
+}
 /* Set which of the four TX / RX chains provided by AD9361 are active.
  *
  * AD9361 provides two sets of chains, Side A and Side B. Each side
@@ -2104,7 +2109,7 @@ double ad9361_device_t::tune(direction_t direction, const double value)
         _io_iface->poke8(0x014, 0x21);
     }
 
-    return tune_freq;
+    return get_freq(direction);
 }
 
 /* Get the current RX or TX frequency. */
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.h b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
index 2a81118ce..b3256b4c4 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.h
@@ -161,6 +161,9 @@ public:
     /* Set SPI interface */
     void set_io_iface(ad9361_io::sptr io_iface);
 
+    /* Get the current clock rate. */
+    double get_clock_rate();
+
     /* This function sets the RX / TX rate between AD9361 and the FPGA, and
      * thus determines the interpolation / decimation required in the FPGA to
      * achieve the user's requested rate.