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| author | Neel Pandeya <neel.pandeya@ettus.com> | 2015-03-23 16:10:04 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2015-03-30 10:33:47 -0700 |
| commit | 1fe6a3a8aa4ae6af023552786a190f2d98de8a87 (patch) | |
| tree | 788918d4b78ef93a971c5d8366df4d0a54b117c7 | |
| parent | 2df1b69dcc38effa5ba66eab86341df9a7a04733 (diff) | |
| download | uhd-1fe6a3a8aa4ae6af023552786a190f2d98de8a87.tar.gz uhd-1fe6a3a8aa4ae6af023552786a190f2d98de8a87.tar.bz2 uhd-1fe6a3a8aa4ae6af023552786a190f2d98de8a87.zip | |
x300: Fix for Bug #714: Phase wobble across four channels on two devices
- Increased filter loop bandwith on clock control chip
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index 247c10ac4..b59247d53 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -190,7 +190,7 @@ void set_master_clock_rate(double clock_rate) { // PLL1 - 2 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 100; _lmk04816_regs.PLL1_R_27 = 5; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 96 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 5; |